def generate_project(self):
""" copy template drivers files """
project = self.project
op_sys = self.name
if op_sys is None:
raise PodError("Operating system must be selected", 0)
for component in project.instances:
if component.num == "0":
driver_template = component.get_driver_template(op_sys)
if driver_template is not None:
if sy.dir_exist(self.project.projectpath + DRIVERSPATH +
"/" + component.name):
DISPLAY.msg("Driver directory for " +
component.name +
" allready exist. suppressing it")
sy.rm_dir(self.project.projectpath + DRIVERSPATH +
"/" + component.name)
DISPLAY.msg("Create directory for " +
component.name + " driver")
# create component directory
sy.mkdir(self.project.projectpath +
DRIVERSPATH + "/" +
component.name)
else:
DISPLAY.msg("No driver for " + component.name)
def generate_project(self):
""" copy all hdl file in synthesis project directory
"""
for component in self.parent.instances:
if component.num == "0":
# Make directory
compdir = self.parent.projectpath +\
SYNTHESISPATH + "/" +\
component.name
if sy.dir_exist(compdir):
DISPLAY.msg("Directory " + compdir +
" exist, will be deleted")
sy.rm_dir(compdir)
sy.mkdir(compdir)
DISPLAY.msg("Make directory for " + component.name)
# copy hdl files
for hdlfile in component.hdl_files:
try:
sy.cp_file(
self.parent.projectpath + COMPONENTSPATH + "/" +
component.instancename + "/hdl/" +
hdlfile.filename, compdir + "/")
except IOError as error:
print(DISPLAY)
raise PodError(str(error), 0)
def generate_project(self):
""" copy all hdl file in synthesis project directory
"""
for component in self.parent.instances:
if component.num == "0":
# Make directory
compdir = self.parent.projectpath +\
SYNTHESISPATH + "/" +\
component.name
if sy.dir_exist(compdir):
DISPLAY.msg("Directory " + compdir +
" exist, will be deleted")
sy.rm_dir(compdir)
sy.mkdir(compdir)
DISPLAY.msg("Make directory for " + component.name)
# copy hdl files
for hdlfile in component.hdl_files:
try:
sy.cp_file(self.parent.projectpath +
COMPONENTSPATH + "/" +
component.instancename +
"/hdl/" + hdlfile.filename,
compdir + "/")
except IOError as error:
print(DISPLAY)
raise PodError(str(error), 0)
def save(self):
""" Save component in project directory files """
if not sy.dir_exist(self.parent.projectpath + COMPONENTSPATH + "/" +
self.instancename):
sy.mkdir(self.parent.projectpath + COMPONENTSPATH + "/" +
self.instancename)
self.save_xml(self.parent.projectpath + COMPONENTSPATH + "/" +
self.instancename + "/" + self.instancename + ".xml")
def save(self):
""" Save component in project directory files """
if not sy.dir_exist(self.parent.projectpath + COMPONENTSPATH +
"/" + self.instancename):
sy.mkdir(self.parent.projectpath + COMPONENTSPATH +
"/" + self.instancename)
self.save_xml(self.parent.projectpath + COMPONENTSPATH + "/" +
self.instancename + "/" +
self.instancename + ".xml")
def generate_intercon(masterinterface, intercon):
"""Generate intercon VHDL code for wishbone16 bus
"""
masterinstance = masterinterface.parent
project = masterinstance.parent
# comment and header
VHDLcode = header(SETTINGS.author, intercon)
# entity
VHDLcode = VHDLcode + entity(intercon)
VHDLcode = VHDLcode + architectureHead(masterinterface, intercon)
VHDLcode = VHDLcode + genCaseByteEnable(masterinterface)
VHDLcode = VHDLcode + gen_byte_enable(masterinterface)
listslave = masterinterface.slaves
listinterfacesyscon = []
for slaveinstance in [slave.get_instance() for slave in listslave]:
listinterfacesyscon.append(slaveinstance.get_one_syscon())
listinterfacesyscon.append(masterinstance.get_one_syscon())
# Clock and Reset connection
VHDLcode = VHDLcode + connectClockandReset(masterinterface,
intercon)
# address decoding
VHDLcode = VHDLcode + addressdecoding(masterinterface,
masterinstance, intercon)
# controls slaves
VHDLcode = VHDLcode + controlslave(masterinterface, intercon)
# controls master
VHDLcode = VHDLcode + controlmaster(masterinterface, intercon)
# readdata mux
VHDLcode = VHDLcode + selectWrite(masterinterface, intercon)
# Foot
VHDLcode = VHDLcode + architectureFoot(intercon)
# saving
if not sy.dir_exist(SETTINGS.projectpath +
COMPONENTSPATH + "/" +
intercon.instancename + "/" + HDLDIR):
sy.mkdir(SETTINGS.projectpath +
COMPONENTSPATH + "/" +
intercon.instancename + "/" + HDLDIR)
afile = open(SETTINGS.projectpath + COMPONENTSPATH + "/" +
intercon.instancename +
"/" + HDLDIR + "/" + intercon.instancename + VHDLEXT,
"w")
afile.write(VHDLcode)
afile.close()
# hdl file path
hdl = HdlFile(intercon,
filename=intercon.instancename + VHDLEXT,
istop=1, scope="both")
intercon.add_hdl_file(hdl)
return VHDLcode
def generate_intercon(masterinterface, intercon):
"""Generate intercon VHDL code for wishbone16 bus
"""
masterinstance = masterinterface.parent
project = masterinstance.parent
# comment and header
VHDLcode = header(SETTINGS.author, intercon)
# entity
VHDLcode = VHDLcode + entity(intercon)
VHDLcode = VHDLcode + architectureHead(masterinterface, intercon)
listslave = masterinterface.slaves
listinterfacesyscon = []
for slaveinstance in [slave.get_instance() for slave in listslave]:
listinterfacesyscon.append(slaveinstance.get_one_syscon())
listinterfacesyscon.append(masterinstance.get_one_syscon())
# Clock and Reset connection
VHDLcode = VHDLcode + connectClockandReset(masterinterface,
intercon)
# address decoding
VHDLcode = VHDLcode + addressdecoding(masterinterface,
masterinstance, intercon)
# controls slaves
VHDLcode = VHDLcode + controlslave(masterinterface, intercon)
# controls master
VHDLcode = VHDLcode + controlmaster(masterinterface, intercon)
# Foot
VHDLcode = VHDLcode + architectureFoot(intercon)
# saving
if not sy.dir_exist(SETTINGS.projectpath +
COMPONENTSPATH + "/" +
intercon.instancename + "/" + HDLDIR):
sy.mkdir(SETTINGS.projectpath +
COMPONENTSPATH + "/" +
intercon.instancename + "/" + HDLDIR)
afile = open(SETTINGS.projectpath + COMPONENTSPATH + "/" +
intercon.instancename +
"/" + HDLDIR + "/" + intercon.instancename + VHDLEXT,
"w")
afile.write(VHDLcode)
afile.close()
# hdl file path
hdl = HdlFile(intercon,
filename=intercon.instancename + VHDLEXT,
istop=1, scope="both")
intercon.add_hdl_file(hdl)
return VHDLcode
def generate_intercon(masterinterface, intercon):
"""Generate intercon VHDL code for axi4lite bus
"""
masterinstance = masterinterface.parent
# comment and header
vhdl_code = header(SETTINGS.author, intercon)
# entity
vhdl_code += entity(intercon)
vhdl_code += architecture_head(masterinterface, intercon)
vhdl_code += gen_case_byte_enable(masterinterface)
listslave = masterinterface.slaves
listinterfacesyscon = []
for slaveinstance in [slave.get_instance() for slave in listslave]:
listinterfacesyscon.append(slaveinstance.get_one_syscon())
listinterfacesyscon.append(masterinstance.get_one_syscon())
# Clock and Reset connection
vhdl_code += connect_clock_and_reset(masterinterface)
# address decoding
vhdl_code += addressdecoding(masterinterface, masterinstance)
# controls slaves
vhdl_code += controlslave(masterinterface)
# controls master
vhdl_code += controlmaster(masterinterface)
# Foot
vhdl_code += architecture_foot(intercon)
# saving
if not sy.dir_exist(SETTINGS.projectpath +
COMPONENTSPATH + "/" +
intercon.instancename + "/" + HDLDIR):
sy.mkdir(SETTINGS.projectpath +
COMPONENTSPATH + "/" +
intercon.instancename + "/" + HDLDIR)
afile = open(SETTINGS.projectpath + COMPONENTSPATH + "/" +
intercon.instancename +
"/" + HDLDIR + "/" + intercon.instancename + VHDLEXT,
"w")
afile.write(vhdl_code)
afile.close()
# hdl file path
hdl = HdlFile(intercon,
filename=intercon.instancename + VHDLEXT,
istop=1, scope="both")
intercon.add_hdl_file(hdl)
return vhdl_code
def generate_project(self):
""" copy template drivers files """
project = self.project
op_sys = self.name
if op_sys is None:
raise PodError("Operating system must be selected", 0)
for component in project.instances:
if component.num == "0":
driver_template = component.get_driver_template(op_sys)
if driver_template is not None:
if sy.dir_exist(self.project.projectpath + DRIVERSPATH +
"/" + component.name):
DISPLAY.msg("Driver directory for " + component.name +
" allready exist. suppressing it")
sy.rm_dir(self.project.projectpath + DRIVERSPATH +
"/" + component.name)
DISPLAY.msg("Create directory for " + component.name +
" driver")
# create component directory
sy.mkdir(self.project.projectpath + DRIVERSPATH + "/" +
component.name)
else:
DISPLAY.msg("No driver for " + component.name)
def generate_intercon(masterinterface, intercon):
"""Generate intercon VHDL code for wishbone16 bus
"""
masterinstance = masterinterface.parent
project = masterinstance.parent
# comment and header
VHDLcode = header(SETTINGS.author, intercon)
# entity
VHDLcode = VHDLcode + entity(intercon)
VHDLcode = VHDLcode + architectureHead(masterinterface, intercon)
# Clock and Reset connection
VHDLcode = VHDLcode + connectClockandReset(masterinterface, intercon)
# Foot
VHDLcode = VHDLcode + architectureFoot(intercon)
# saving
if not sy.dir_exist(SETTINGS.projectpath +
COMPONENTSPATH + "/" +
intercon.instancename + "/" + HDLDIR):
sy.mkdir(SETTINGS.projectpath +
COMPONENTSPATH + "/" +
intercon.instancename + "/" + HDLDIR)
afile = open(SETTINGS.projectpath + COMPONENTSPATH + "/" +
intercon.instancename +
"/" + HDLDIR + "/" + intercon.instancename + VHDLEXT,
"w")
afile.write(VHDLcode)
afile.close()
# hdl file path
hdl = HdlFile(intercon,
filename=intercon.instancename + VHDLEXT,
istop=1, scope="both")
intercon.add_hdl_file(hdl)
return VHDLcode
def create_project(self, name):
""" Create a project """
if sy.dir_exist(self.projectpath):
raise PodError("Can't create project, directory " +
self.projectpath +
" already exists", 0)
sy.mkdir(self.projectpath)
sy.mkdir(self.projectpath + BINARYPROJECTPATH)
sy.mkdir(self.projectpath + COMPONENTSPATH)
sy.mkdir(self.projectpath + OBJSPATH)
sy.mkdir(self.projectpath + SIMULATIONPATH)
sy.mkdir(self.projectpath + SYNTHESISPATH)
sy.mkdir(self.projectpath + DRIVERSPATH)
self.create_xml("project")
self.name = name
self.version = "1.0"
self.void = 0
self.save()
def create_project(self, name):
""" Create a project """
if sy.dir_exist(self.projectpath):
raise PodError(
"Can't create project, directory " + self.projectpath +
" already exists", 0)
sy.mkdir(self.projectpath)
sy.mkdir(self.projectpath + BINARYPROJECTPATH)
sy.mkdir(self.projectpath + COMPONENTSPATH)
sy.mkdir(self.projectpath + OBJSPATH)
sy.mkdir(self.projectpath + SIMULATIONPATH)
sy.mkdir(self.projectpath + SYNTHESISPATH)
sy.mkdir(self.projectpath + DRIVERSPATH)
self.create_xml("project")
self.name = name
self.version = "1.0"
self.void = 0
self.save()