class t_ParamStruct(Testable):
'''|
| Automatically generated. Do not modify this file.
|________'''
pihdf.head("T E S T S")
pihdf.info("Using myhdl version " + myhdl.__version__)
pihdf.info("Using pihdf version " + pihdf.__version__ + '\n')
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_tx = []
self.res_tx = []
self.cond_sim_end = {}
self.tst_data = { "cond_tx":self.cond_tx,\
"res_tx":self.res_tx,\
"cond_sim_end": self.cond_sim_end }
self.ref_tx = []
self.ref_data = {"tx": (self.ref_tx, self.res_tx)}
# Automatically executed BEFORE every test case
def setUp(self):
print ""
# Automatically executed AFTER every test case
def tearDown(self):
print ""
self.cond_tx = []
self.res_tx = []
self.ref_tx = []
# Data has been previously generated and written to files
def use_data_from_files(self):
self.res_tx.append({"file": self.test_path + "/vectors/my_tx.tvr"})
self.ref_tx.append({"file": self.test_path + "/vectors/tx.tvr"})
self.checkfiles = True
self.run_it()
# Run the simulation and check the results
def run_it(self, checkfiles=False):
self.check_config("ParamStruct")
ParamStruct_dut = ParamStruct(IMPL=self.models)
ParamStruct_dut.Simulate(tb_config=self.tb_config,
tst_data=self.tst_data,
verbose=self.verbose,
dut_params=self.dut_params)
ParamStruct_dut.clean()
self.check_results()
class t_STAvln_tb(Testable):
'''|
| Automatically generated. Do not modify this file.
|________'''
pihdf.head("T E S T S")
pihdf.info("Using myhdl version " + myhdl.__version__)
pihdf.info("Using pihdf version " + pihdf.__version__ + '\n')
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_rx16 = []
self.stim_rx16 = []
self.cond_tx16 = []
self.res_tx16 = []
self.cond_rx32 = []
self.stim_rx32 = []
self.cond_tx32 = []
self.res_tx32 = []
self.cond_rx64 = []
self.stim_rx64 = []
self.cond_tx64 = []
self.res_tx64 = []
self.cond_ipg_rx16 = []
self.res_ipg_rx16 = []
self.cond_ipg_tx16 = []
self.res_ipg_tx16 = []
self.cond_sim_end = {}
self.tst_data = { "cond_rx16":self.cond_rx16,\
"stim_rx16":self.stim_rx16,\
"cond_tx16":self.cond_tx16,\
"res_tx16":self.res_tx16,\
"cond_rx32":self.cond_rx32,\
"stim_rx32":self.stim_rx32,\
"cond_tx32":self.cond_tx32,\
"res_tx32":self.res_tx32,\
"cond_rx64":self.cond_rx64,\
"stim_rx64":self.stim_rx64,\
"cond_tx64":self.cond_tx64,\
"res_tx64":self.res_tx64,\
"cond_ipg_rx16":self.cond_ipg_rx16,\
"res_ipg_rx16":self.res_ipg_rx16,\
"cond_ipg_tx16":self.cond_ipg_tx16,\
"res_ipg_tx16":self.res_ipg_tx16,\
"cond_sim_end": self.cond_sim_end }
self.ref_tx16 = []
self.ref_tx32 = []
self.ref_tx64 = []
self.ref_ipg_rx16 = []
self.ref_ipg_tx16 = []
self.ref_data = { "tx16":(self.ref_tx16, self.res_tx16),\
"tx32":(self.ref_tx32, self.res_tx32),\
"tx64":(self.ref_tx64, self.res_tx64),\
"ipg_rx16":(self.ref_ipg_rx16, self.res_ipg_rx16),\
"ipg_tx16":(self.ref_ipg_tx16, self.res_ipg_tx16) }
# Automatically executed BEFORE every test case
def setUp(self):
print ""
# Automatically executed AFTER every test case
def tearDown(self):
print ""
self.cond_rx16 = []
self.stim_rx16 = []
self.cond_tx16 = []
self.res_tx16 = []
self.ref_tx16 = []
self.cond_rx32 = []
self.stim_rx32 = []
self.cond_tx32 = []
self.res_tx32 = []
self.ref_tx32 = []
self.cond_rx64 = []
self.stim_rx64 = []
self.cond_tx64 = []
self.res_tx64 = []
self.ref_tx64 = []
self.cond_ipg_rx16 = []
self.res_ipg_rx16 = []
self.ref_ipg_rx16 = []
self.cond_ipg_tx16 = []
self.res_ipg_tx16 = []
self.ref_ipg_tx16 = []
# Data has been previously generated and written to files
def use_data_from_files(self):
self.stim_rx16.append({"file": self.test_path + "/vectors/rx16.tvr"})
self.res_tx16.append({"file": self.test_path + "/vectors/my_tx16.tvr"})
self.ref_tx16.append({"file": self.test_path + "/vectors/tx16.tvr"})
self.stim_rx32.append({"file": self.test_path + "/vectors/rx32.tvr"})
self.res_tx32.append({"file": self.test_path + "/vectors/my_tx32.tvr"})
self.ref_tx32.append({"file": self.test_path + "/vectors/tx32.tvr"})
self.stim_rx64.append({"file": self.test_path + "/vectors/rx64.tvr"})
self.res_tx64.append({"file": self.test_path + "/vectors/my_tx64.tvr"})
self.ref_tx64.append({"file": self.test_path + "/vectors/tx64.tvr"})
self.res_ipg_rx16.append(
{"file": self.test_path + "/vectors/my_ipg_rx16.tvr"})
self.ref_ipg_rx16.append(
{"file": self.test_path + "/vectors/ipg_rx16.tvr"})
self.res_ipg_tx16.append(
{"file": self.test_path + "/vectors/my_ipg_tx16.tvr"})
self.ref_ipg_tx16.append(
{"file": self.test_path + "/vectors/ipg_tx16.tvr"})
self.checkfiles = True
self.run_it()
# Run the simulation and check the results
def run_it(self, checkfiles=False):
self.check_config("STAvln_tb")
STAvln_tb_dut = STAvln_tb(IMPL=self.models)
STAvln_tb_dut.Simulate(tb_config=self.tb_config,
tst_data=self.tst_data,
verbose=self.verbose)
STAvln_tb_dut.clean()
self.check_results()
class t_RegFile_tb(Testable):
'''|
| Automatically generated. Do not modify this file.
|________'''
pihdf.head("T E S T S")
pihdf.info("Using myhdl version " + myhdl.__version__)
pihdf.info("Using pihdf version " + pihdf.__version__ + '\n')
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_simple_bus_wa_wd = []
self.stim_simple_bus_wa_wd = []
self.cond_simple_bus_raddr = []
self.stim_simple_bus_raddr = []
self.cond_simple_bus_rdata = []
self.res_simple_bus_rdata = []
self.cond_sim_end = {}
self.tst_data = { "cond_simple_bus_wa_wd":self.cond_simple_bus_wa_wd,\
"stim_simple_bus_wa_wd":self.stim_simple_bus_wa_wd,\
"cond_simple_bus_raddr":self.cond_simple_bus_raddr,\
"stim_simple_bus_raddr":self.stim_simple_bus_raddr,\
"cond_simple_bus_rdata":self.cond_simple_bus_rdata,\
"res_simple_bus_rdata":self.res_simple_bus_rdata,\
"cond_sim_end": self.cond_sim_end }
self.ref_simple_bus_rdata = []
self.ref_data = {
"simple_bus_rdata":
(self.ref_simple_bus_rdata, self.res_simple_bus_rdata)
}
# Automatically executed BEFORE every test case
def setUp(self):
print ""
# Automatically executed AFTER every test case
def tearDown(self):
print ""
self.cond_simple_bus_wa_wd = []
self.stim_simple_bus_wa_wd = []
self.cond_simple_bus_raddr = []
self.stim_simple_bus_raddr = []
self.cond_simple_bus_rdata = []
self.res_simple_bus_rdata = []
self.ref_simple_bus_rdata = []
# Data has been previously generated and written to files
def use_data_from_files(self):
self.stim_simple_bus_wa_wd.append(
{"file": self.test_path + "/vectors/simple_bus_wa_wd.tvr"})
self.stim_simple_bus_raddr.append(
{"file": self.test_path + "/vectors/simple_bus_raddr.tvr"})
self.res_simple_bus_rdata.append(
{"file": self.test_path + "/vectors/my_simple_bus_rdata.tvr"})
self.ref_simple_bus_rdata.append(
{"file": self.test_path + "/vectors/simple_bus_rdata.tvr"})
self.checkfiles = True
self.run_it()
# Run the simulation and check the results
def run_it(self, checkfiles=False):
self.check_config("RegFile_tb")
RegFile_tb_dut = RegFile_tb(IMPL=self.models)
RegFile_tb_dut.Simulate(tb_config=self.tb_config,
tst_data=self.tst_data,
verbose=self.verbose)
RegFile_tb_dut.clean()
self.check_results()
class t_submodule_rx(Testable):
'''|
| Automatically generated. Do not modify this file.
|________'''
pihdf.head("T E S T S")
pihdf.info("Using myhdl version " + myhdl.__version__)
pihdf.info("Using pihdf version " + pihdf.__version__ + '\n')
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_rx_width = []
self.stim_rx_width = []
self.cond_tx_width = []
self.res_tx_width = []
self.cond_rx_width1 = []
self.stim_rx_width1 = []
self.cond_tx_width1 = []
self.res_tx_width1 = []
self.cond_rx_fields = []
self.stim_rx_fields = []
self.cond_tx_fields = []
self.res_tx_fields = []
self.cond_rx_width_buf = []
self.stim_rx_width_buf = []
self.cond_tx_width_buf = []
self.res_tx_width_buf = []
self.cond_rx_width1_buf = []
self.stim_rx_width1_buf = []
self.cond_tx_width1_buf = []
self.res_tx_width1_buf = []
self.cond_rx_fields_buf = []
self.stim_rx_fields_buf = []
self.cond_tx_fields_buf = []
self.res_tx_fields_buf = []
self.cond_rx_push = []
self.stim_rx_push = []
self.cond_rx_terminate = []
self.stim_rx_terminate = []
self.cond_tx_terminate = []
self.res_tx_terminate = []
self.cond_ipg_rx_width = []
self.res_ipg_rx_width = []
self.cond_sim_end = {}
self.tst_data = { "cond_rx_width":self.cond_rx_width,\
"stim_rx_width":self.stim_rx_width,\
"cond_tx_width":self.cond_tx_width,\
"res_tx_width":self.res_tx_width,\
"cond_rx_width1":self.cond_rx_width1,\
"stim_rx_width1":self.stim_rx_width1,\
"cond_tx_width1":self.cond_tx_width1,\
"res_tx_width1":self.res_tx_width1,\
"cond_rx_fields":self.cond_rx_fields,\
"stim_rx_fields":self.stim_rx_fields,\
"cond_tx_fields":self.cond_tx_fields,\
"res_tx_fields":self.res_tx_fields,\
"cond_rx_width_buf":self.cond_rx_width_buf,\
"stim_rx_width_buf":self.stim_rx_width_buf,\
"cond_tx_width_buf":self.cond_tx_width_buf,\
"res_tx_width_buf":self.res_tx_width_buf,\
"cond_rx_width1_buf":self.cond_rx_width1_buf,\
"stim_rx_width1_buf":self.stim_rx_width1_buf,\
"cond_tx_width1_buf":self.cond_tx_width1_buf,\
"res_tx_width1_buf":self.res_tx_width1_buf,\
"cond_rx_fields_buf":self.cond_rx_fields_buf,\
"stim_rx_fields_buf":self.stim_rx_fields_buf,\
"cond_tx_fields_buf":self.cond_tx_fields_buf,\
"res_tx_fields_buf":self.res_tx_fields_buf,\
"cond_rx_push":self.cond_rx_push,\
"stim_rx_push":self.stim_rx_push,\
"cond_rx_terminate":self.cond_rx_terminate,\
"stim_rx_terminate":self.stim_rx_terminate,\
"cond_tx_terminate":self.cond_tx_terminate,\
"res_tx_terminate":self.res_tx_terminate,\
"cond_ipg_rx_width":self.cond_ipg_rx_width,\
"res_ipg_rx_width":self.res_ipg_rx_width,\
"cond_sim_end": self.cond_sim_end }
self.ref_tx_width = []
self.ref_tx_width1 = []
self.ref_tx_fields = []
self.ref_tx_width_buf = []
self.ref_tx_width1_buf = []
self.ref_tx_fields_buf = []
self.ref_tx_terminate = []
self.ref_ipg_rx_width = []
self.ref_data = { "tx_width":(self.ref_tx_width, self.res_tx_width),\
"tx_width1":(self.ref_tx_width1, self.res_tx_width1),\
"tx_fields":(self.ref_tx_fields, self.res_tx_fields),\
"tx_width_buf":(self.ref_tx_width_buf, self.res_tx_width_buf),\
"tx_width1_buf":(self.ref_tx_width1_buf, self.res_tx_width1_buf),\
"tx_fields_buf":(self.ref_tx_fields_buf, self.res_tx_fields_buf),\
"tx_terminate":(self.ref_tx_terminate, self.res_tx_terminate),\
"ipg_rx_width":(self.ref_ipg_rx_width, self.res_ipg_rx_width) }
# Automatically executed BEFORE every test case
def setUp(self):
print ""
# Automatically executed AFTER every test case
def tearDown(self):
print ""
self.cond_rx_width = []
self.stim_rx_width = []
self.cond_tx_width = []
self.res_tx_width = []
self.ref_tx_width = []
self.cond_rx_width1 = []
self.stim_rx_width1 = []
self.cond_tx_width1 = []
self.res_tx_width1 = []
self.ref_tx_width1 = []
self.cond_rx_fields = []
self.stim_rx_fields = []
self.cond_tx_fields = []
self.res_tx_fields = []
self.ref_tx_fields = []
self.cond_rx_width_buf = []
self.stim_rx_width_buf = []
self.cond_tx_width_buf = []
self.res_tx_width_buf = []
self.ref_tx_width_buf = []
self.cond_rx_width1_buf = []
self.stim_rx_width1_buf = []
self.cond_tx_width1_buf = []
self.res_tx_width1_buf = []
self.ref_tx_width1_buf = []
self.cond_rx_fields_buf = []
self.stim_rx_fields_buf = []
self.cond_tx_fields_buf = []
self.res_tx_fields_buf = []
self.ref_tx_fields_buf = []
self.cond_rx_push = []
self.stim_rx_push = []
self.cond_rx_terminate = []
self.stim_rx_terminate = []
self.cond_tx_terminate = []
self.res_tx_terminate = []
self.ref_tx_terminate = []
self.cond_ipg_rx_width = []
self.res_ipg_rx_width = []
self.ref_ipg_rx_width = []
# Data has been previously generated and written to files
def use_data_from_files(self):
self.stim_rx_width.append(
{"file": self.test_path + "/vectors/rx_width.tvr"})
self.res_tx_width.append(
{"file": self.test_path + "/vectors/my_tx_width.tvr"})
self.ref_tx_width.append(
{"file": self.test_path + "/vectors/tx_width.tvr"})
self.stim_rx_width1.append(
{"file": self.test_path + "/vectors/rx_width1.tvr"})
self.res_tx_width1.append(
{"file": self.test_path + "/vectors/my_tx_width1.tvr"})
self.ref_tx_width1.append(
{"file": self.test_path + "/vectors/tx_width1.tvr"})
self.stim_rx_fields.append(
{"file": self.test_path + "/vectors/rx_fields.tvr"})
self.res_tx_fields.append(
{"file": self.test_path + "/vectors/my_tx_fields.tvr"})
self.ref_tx_fields.append(
{"file": self.test_path + "/vectors/tx_fields.tvr"})
self.stim_rx_width_buf.append(
{"file": self.test_path + "/vectors/rx_width_buf.tvr"})
self.res_tx_width_buf.append(
{"file": self.test_path + "/vectors/my_tx_width_buf.tvr"})
self.ref_tx_width_buf.append(
{"file": self.test_path + "/vectors/tx_width_buf.tvr"})
self.stim_rx_width1_buf.append(
{"file": self.test_path + "/vectors/rx_width1_buf.tvr"})
self.res_tx_width1_buf.append(
{"file": self.test_path + "/vectors/my_tx_width1_buf.tvr"})
self.ref_tx_width1_buf.append(
{"file": self.test_path + "/vectors/tx_width1_buf.tvr"})
self.stim_rx_fields_buf.append(
{"file": self.test_path + "/vectors/rx_fields_buf.tvr"})
self.res_tx_fields_buf.append(
{"file": self.test_path + "/vectors/my_tx_fields_buf.tvr"})
self.ref_tx_fields_buf.append(
{"file": self.test_path + "/vectors/tx_fields_buf.tvr"})
self.stim_rx_push.append(
{"file": self.test_path + "/vectors/rx_push.tvr"})
self.stim_rx_terminate.append(
{"file": self.test_path + "/vectors/rx_terminate.tvr"})
self.res_tx_terminate.append(
{"file": self.test_path + "/vectors/my_tx_terminate.tvr"})
self.ref_tx_terminate.append(
{"file": self.test_path + "/vectors/tx_terminate.tvr"})
self.res_ipg_rx_width.append(
{"file": self.test_path + "/vectors/my_ipg_rx_width.tvr"})
self.ref_ipg_rx_width.append(
{"file": self.test_path + "/vectors/ipg_rx_width.tvr"})
self.checkfiles = True
self.run_it()
# Run the simulation and check the results
def run_it(self, checkfiles=False):
self.check_config("submodule_rx")
submodule_rx_dut = submodule_rx(IMPL=self.models)
submodule_rx_dut.Simulate(tb_config=self.tb_config,
tst_data=self.tst_data,
verbose=self.verbose)
submodule_rx_dut.clean()
self.check_results()
class t_hsd_struct(Testable):
'''|
| Automatically generated. Do not modify this file.
|________'''
pihdf.head("T E S T S")
pihdf.info("Using myhdl version " + myhdl.__version__)
pihdf.info("Using pihdf version " + pihdf.__version__ + '\n')
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_mode_1 = []
self.stim_mode_1 = []
self.cond_mode_2 = []
self.stim_mode_2 = []
self.cond_LEDs = []
self.res_LEDs = []
self.cond_LED_rdy_en = []
self.res_LED_rdy_en = []
self.cond_LED_rdy_buff = []
self.res_LED_rdy_buff = []
self.cond_LED_rdy_out = []
self.res_LED_rdy_out = []
self.cond_sim_end = {}
self.tst_data = { "cond_mode_1":self.cond_mode_1,\
"stim_mode_1":self.stim_mode_1,\
"cond_mode_2":self.cond_mode_2,\
"stim_mode_2":self.stim_mode_2,\
"cond_LEDs":self.cond_LEDs,\
"res_LEDs":self.res_LEDs,\
"cond_LED_rdy_en":self.cond_LED_rdy_en,\
"res_LED_rdy_en":self.res_LED_rdy_en,\
"cond_LED_rdy_buff":self.cond_LED_rdy_buff,\
"res_LED_rdy_buff":self.res_LED_rdy_buff,\
"cond_LED_rdy_out":self.cond_LED_rdy_out,\
"res_LED_rdy_out":self.res_LED_rdy_out,\
"cond_sim_end": self.cond_sim_end }
self.ref_LEDs = []
self.ref_LED_rdy_en = []
self.ref_LED_rdy_buff = []
self.ref_LED_rdy_out = []
self.ref_data = { "LEDs":(self.ref_LEDs, self.res_LEDs),\
"LED_rdy_en":(self.ref_LED_rdy_en, self.res_LED_rdy_en),\
"LED_rdy_buff":(self.ref_LED_rdy_buff, self.res_LED_rdy_buff),\
"LED_rdy_out":(self.ref_LED_rdy_out, self.res_LED_rdy_out) }
# Automatically executed BEFORE every test case
def setUp(self):
print ""
# Automatically executed AFTER every test case
def tearDown(self):
print ""
self.cond_mode_1 = []
self.stim_mode_1 = []
self.cond_mode_2 = []
self.stim_mode_2 = []
self.cond_LEDs = []
self.res_LEDs = []
self.ref_LEDs = []
self.cond_LED_rdy_en = []
self.res_LED_rdy_en = []
self.ref_LED_rdy_en = []
self.cond_LED_rdy_buff = []
self.res_LED_rdy_buff = []
self.ref_LED_rdy_buff = []
self.cond_LED_rdy_out = []
self.res_LED_rdy_out = []
self.ref_LED_rdy_out = []
# Data has been previously generated and written to files
def use_data_from_files(self):
self.stim_mode_1.append(
{"file": self.test_path + "/vectors/mode_1.tvr"})
self.stim_mode_2.append(
{"file": self.test_path + "/vectors/mode_2.tvr"})
self.res_LEDs.append({"file": self.test_path + "/vectors/my_LEDs.tvr"})
self.ref_LEDs.append({"file": self.test_path + "/vectors/LEDs.tvr"})
self.res_LED_rdy_en.append(
{"file": self.test_path + "/vectors/my_LED_rdy_en.tvr"})
self.ref_LED_rdy_en.append(
{"file": self.test_path + "/vectors/LED_rdy_en.tvr"})
self.res_LED_rdy_buff.append(
{"file": self.test_path + "/vectors/my_LED_rdy_buff.tvr"})
self.ref_LED_rdy_buff.append(
{"file": self.test_path + "/vectors/LED_rdy_buff.tvr"})
self.res_LED_rdy_out.append(
{"file": self.test_path + "/vectors/my_LED_rdy_out.tvr"})
self.ref_LED_rdy_out.append(
{"file": self.test_path + "/vectors/LED_rdy_out.tvr"})
self.checkfiles = True
self.run_it()
# Run the simulation and check the results
def run_it(self, checkfiles=False):
self.check_config("hsd_struct")
hsd_struct_dut = hsd_struct(IMPL=self.models)
hsd_struct_dut.Simulate(tb_config=self.tb_config,
tst_data=self.tst_data,
verbose=self.verbose,
dut_params=self.dut_params)
hsd_struct_dut.clean()
self.check_results()
