def create_nand(self, inputs):
""" Create the NAND for the predecode input stage """
if inputs == 2:
self.nand = pnand2()
elif inputs == 3:
self.nand = pnand3()
else:
debug.error("Invalid number of predecode inputs.", -1)
def add_layout(self):
self.inv = pinv()
self.add_mod(self.inv)
self.inv_no_output = pinv(route_output=False)
self.add_mod(self.inv_no_output)
self.nand2 = pnand2()
self.add_mod(self.nand2)
def add_modules(self):
self.inv = pinv()
self.add_mod(self.inv)
self.nand2 = pnand2()
self.add_mod(self.nand2)
self.nand3 = pnand3()
self.add_mod(self.nand3)
self.add_decoders()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pnand2
import tech
debug.info(2, "Checking 2-input nand gate")
tx = pnand2.pnand2(name="pnand2", size=1)
self.local_check(tx)
globals.end_openram()
def add_modules(self):
# This is just used for measurements,
# so don't add the module
self.inv = pinv()
self.add_mod(self.inv)
self.inv_no_output = pinv(route_output=False)
self.add_mod(self.inv_no_output)
self.nand2 = pnand2()
self.add_mod(self.nand2)
def add_modules(self):
self.inv = pinv()
self.add_mod(self.inv)
self.nand2 = pnand2()
self.add_mod(self.nand2)
self.nand3 = pnand3()
self.add_mod(self.nand3)
# CREATION OF PRE-DECODER
self.pre2_4 = pre2x4()
self.add_mod(self.pre2_4)
self.pre3_8 = pre3x8()
self.add_mod(self.pre3_8)
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import pnand2
import tech
debug.info(2, "Checking 2-input nand gate")
tx = pnand2.pnand2(size=1)
self.local_check(tx)
OPTS.check_lvsdrc = True
globals.end_openram()
def add_modules(self):
""" Create modules for later instantiation """
# 1x Inverter
self.inv = pinv()
self.add_mod(self.inv)
# 4x Inverter
self.inv4x = pinv(4)
self.add_mod(self.inv4x)
self.nor2 = pnor2()
self.add_mod(self.nor2)
self.nand2 = pnand2()
self.add_mod(self.nand2)
def create_modules(self):
""" add all the required modules """
input_lst = ["csb", "web", "oeb", "clk"]
output_lst = [
"s_en", "w_en", "tri_en", "tri_en_bar", "clk_bar", "clk_buf"
]
rails = ["vdd", "gnd"]
for pin in input_lst + output_lst + rails:
self.add_pin(pin)
self.nand2 = pnand2()
self.add_mod(self.nand2)
self.nand3 = pnand3()
self.add_mod(self.nand3)
self.nor2 = pnor2()
self.add_mod(self.nor2)
# Special gates: inverters for buffering
self.inv = self.inv1 = pinv(1)
self.add_mod(self.inv1)
self.inv2 = pinv(2)
self.add_mod(self.inv2)
self.inv4 = pinv(4)
self.add_mod(self.inv4)
self.inv8 = pinv(8)
self.add_mod(self.inv8)
self.inv16 = pinv(16)
self.add_mod(self.inv16)
c = reload(__import__(OPTS.ms_flop_array))
ms_flop_array = getattr(c, OPTS.ms_flop_array)
self.msf_control = ms_flop_array(name="msf_control",
columns=3,
word_size=3)
self.add_mod(self.msf_control)
c = reload(__import__(OPTS.replica_bitline))
replica_bitline = getattr(c, OPTS.replica_bitline)
# FIXME: These should be tuned according to the size!
delay_stages = 4 # This should be even so that the delay line is inverting!
delay_fanout = 3
bitcell_loads = int(math.ceil(self.num_rows / 5.0))
self.replica_bitline = replica_bitline(delay_stages, delay_fanout,
bitcell_loads)
self.add_mod(self.replica_bitline)
def create_modules(self):
""" add all the required modules """
input_lst = ["csb", "web", "oeb", "clk"]
output_lst = [
"s_en", "w_en", "tri_en", "tri_en_bar", "clk_bar", "clk_buf"
]
rails = ["vdd", "gnd"]
for pin in input_lst + output_lst + rails:
self.add_pin(pin)
self.nand2 = pnand2()
self.add_mod(self.nand2)
self.nand3 = pnand3()
self.add_mod(self.nand3)
self.nor2 = pnor2()
self.add_mod(self.nor2)
# Special gates: inverters for buffering
self.inv = self.inv1 = pinv(1)
self.add_mod(self.inv1)
self.inv2 = pinv(2)
self.add_mod(self.inv2)
self.inv4 = pinv(4)
self.add_mod(self.inv4)
self.inv8 = pinv(8)
self.add_mod(self.inv8)
self.inv16 = pinv(16)
self.add_mod(self.inv16)
c = reload(__import__(OPTS.config.ms_flop_array))
ms_flop_array = getattr(c, OPTS.config.ms_flop_array)
self.msf_control = ms_flop_array(name="msf_control",
columns=3,
word_size=3)
self.add_mod(self.msf_control)
c = reload(__import__(OPTS.config.replica_bitline))
replica_bitline = getattr(c, OPTS.config.replica_bitline)
self.replica_bitline = replica_bitline(
rows=int(math.ceil(self.num_rows / 10.0)))
self.add_mod(self.replica_bitline)
def add_modules(self):
""" Add all the required modules """
dff = dff_inv()
dff_height = dff.height
self.ctrl_dff_array = dff_inv_array(rows=2, columns=1)
self.add_mod(self.ctrl_dff_array)
self.nand2 = pnand2(height=dff_height)
self.add_mod(self.nand2)
self.nand3 = pnand3(height=dff_height)
self.add_mod(self.nand3)
# Special gates: inverters for buffering
# Size the clock for the number of rows (fanout)
clock_driver_size = max(1, int(self.num_rows / 4))
self.clkbuf = pinvbuf(clock_driver_size, height=dff_height)
self.add_mod(self.clkbuf)
self.inv = self.inv1 = pinv(size=1, height=dff_height)
self.add_mod(self.inv1)
self.inv2 = pinv(size=4, height=dff_height)
self.add_mod(self.inv2)
self.inv8 = pinv(size=16, height=dff_height)
self.add_mod(self.inv8)
from importlib import reload
c = reload(__import__(OPTS.replica_bitline))
replica_bitline = getattr(c, OPTS.replica_bitline)
# FIXME: These should be tuned according to the size!
delay_stages = 4 # Must be non-inverting
delay_fanout = 3 # This can be anything >=2
bitcell_loads = int(math.ceil(self.num_rows / 5.0))
self.replica_bitline = replica_bitline(delay_stages, delay_fanout,
bitcell_loads)
self.add_mod(self.replica_bitline)
