def __init__(self): self.in0 = Port(int, 'in') self.in_valid = Port(bool, 'in') self.out0 = Port(int, 'out') self.out_valid = Port(bool, 'out', init=False) self.start = Port(bool, 'out', init=False) self.append_worker(self.main)
def __init__(self): self.mode = Port(int, 'in', protocol='ready_valid') self.result = Port(int, 'out', protocol='ready_valid') self.a = Object() self.b = Object() self.c = Object() self.append_worker(self.main)
def initialize_1(m): for i in range(10): inp = 'i' + str(i) outp = 'o' + str(i) m.__dict__[inp] = Port(bit, 'in') m.__dict__[outp] = Port(bit, 'out') initialize_2(m)
def __init__(self): self.run = Port(bool, 'in', protocol='ready_valid') self.result = Port(int, 'out', protocol='ready_valid') self.din = Queue(int32, 'in') self.dout = Queue(int32, 'out') self.append_worker(self.mips_main)
def __init__(self): self.clk1 = Port(bit, 'in', init=1) self.clk2 = Port(bit, 'in', init=1) self.out1 = Port(bit, 'out', init=0) self.out2 = Port(bit, 'out', init=0) self.append_worker(self.main) self.append_worker(other_main, self.clk1, self.clk2, self.out2)
class object_if01: def __init__(self): self.mode = Port(int, 'in', protocol='ready_valid') self.result = Port(int, 'out', protocol='ready_valid') self.a = Object() self.b = Object() self.c = Object() self.append_worker(self.main) def read(self, obj0, obj1): x = obj0.read() y = obj1.read() return x - y def main(self): while is_worker_running(): mode = self.mode.rd() ret = 0 if mode == 0: ret = self.read(self.a, self.b) elif mode == 1: ret = self.read(self.b, self.c) elif mode == 2: pass else: ret = self.read(self.c, self.a) self.result.wr(ret)
def __init__(self): self.idata_a = Port(uint16, 'in', protocol='valid') self.idata_b = Port(uint16, 'in', protocol='valid') self.odata_a = Port(uint16, 'out', protocol='ready_valid') self.odata_b = Port(uint16, 'out', protocol='ready_valid') self.append_worker(self.worker, 'foo', self.idata_a, self.odata_a) self.append_worker(self.worker, 'bar', self.idata_b, self.odata_b)
def __init__(self): self.sclk = Port(bit, 'out') self.mosi = Port(bit, 'out') self.miso = Port(bit, 'in') self.cs_n = Port(bit, 'out', init=1) self.data8 = Port(uint8, 'out', protocol='ready_valid') self.append_worker(self.worker)
def __init__(self): self.in0 = Port(int8, 'in') self.in_valid = Port(bit, 'in') self.out0 = Port(int8, 'out') self.out_valid = Port(bit, 'out', init=0) self.start = Port(bit, 'out', init=0) # append this module's worker self.append_worker(self.main)
class io_write_conflict02: def __init__(self): self.p = Port(bool, 'out') self.append_worker(self.w) self.append_worker(self.w) def w(self): self.p.wr(1)
def __init__(self): self.idata = Port(int, 'in', protocol='ready_valid') self.odata = Port(int, 'out', protocol='ready_valid') t0 = Port(int, 'any', protocol='ready_valid') t1 = Port(int, 'any', protocol='ready_valid') self.append_worker(pow, self.idata, t0) self.append_worker(pow, t0, t1) self.append_worker(pow, t1, self.odata)
class port_is_not_used01: def __init__(self): self.p = Port(bool, 'out') self.q = Port(bool, 'out') self.append_worker(self.w) def w(self): self.q.wr(1)
class Protocol02: def __init__(self): self.i = Port(int8, 'in', init=0, protocol='ready_valid') self.o = Port(int8, 'out', init=0, protocol='ready_valid') self.append_worker(self.main) def main(self): t = self.i.rd() self.o.wr(t * t)
def __init__(self): self.status_port = Port(bit32, 'out', init=STATUS_BUSY_FLAG) self.cmd_in = Port(bit32, 'in') self.cmd_reply = Port(bit32, 'out', init=0) self.uart_data_in = Port(bit32, 'in') self.uart_data_out = Port(bit32, 'out') self.uart_bridge = UartBridge() self.append_worker(self.worker)
def make_io_ports(m, size, inports, outports): for i in range(size): inname = 'i' + str(i) outname = 'o' + str(i) inport = Port(int, 'in', protocol=proto) outport = Port(int, 'out', protocol=proto) setattr(m, inname, inport) setattr(m, outname, outport) inports.append(inport) outports.append(outport)
class import13: def __init__(self): self.x = Value self.o = Port(int, 'out', protocol='ready_valid') self.append_worker(self.w) def w(self): while is_worker_running(): for i in range(len(SUB3_GLOBAL_ARRAY)): self.o.wr(self.x + SUB3_GLOBAL_ARRAY[i])
class Submodule: def __init__(self, param): self.i = Port(int8, 'in') self.o = Port(int8, 'out') self.param = param self.append_worker(self.sub_worker) def sub_worker(self): while is_worker_running(): v = self.i.rd() * self.param self.o.wr(v)
def __init__(self): self.rx_data = Port(bit8, 'in') self.rx_ready = Port(bit, 'in') self.rx_idle = Port(bit, 'in') self.tx_start = Port(bit, 'out', 0) self.tx_data = Port(bit8, 'out', 0) self.tx_busy = Port(bit, 'in')
class Protocol01: def __init__(self): self.i = Port(int8, 'in', init=0, protocol='valid') self.o = Port(int8, 'out', init=0, protocol='ready_valid') self.append_worker(self.main) def main(self): # Reading from the "valid" protocol port is blocked until the port becomes 'valid'. t = self.i.rd() # Writing to the 'ready_valid' protocol port makes the port 'valid'. # And if the port is not 'ready', it is blocked until the port becomes 'ready'. self.o.wr(t * t)
class adder: def __init__(self): self.i_a3 = Port(uint3, 'in', protocol='valid') self.i_b3 = Port(uint3, 'in', protocol='valid') self.o_r4 = Port(uint4, 'out', protocol='valid') self.append_worker(self.adder_worker) def adder_worker(self): while polyphony.is_worker_running(): a3: uint4 = self.i_a3.rd() b3: uint4 = self.i_b3.rd() r4: uint4 = a3 + b3 self.o_r4(r4)
class Port02: def __init__(self): self.clk1 = Port(bit, 'in', init=1) self.clk2 = Port(bit, 'in', init=1) self.out1 = Port(bit, 'out', init=0) self.out2 = Port(bit, 'out', init=0) self.append_worker(self.main) self.append_worker(other_main, self.clk1, self.clk2, self.out2) def main(self): #print('main') while is_worker_running(): wait_rising(self.clk1, self.clk2) msg('rising', self.clk1(), self.clk2()) self.out1.wr(1)
class Sub: def __init__(self): self.p = Port(int, 'in') self.append_worker(self.w) def w(self): x = self.p.rd()
def initialize_2(m): for i in range(10): inp = 'i' + str(i) outp = 'o' + str(i) tmp = Port(bit, 'any') m.append_worker(m.worker, 'front' + str(i), m.__dict__[inp], tmp) m.append_worker(m.worker, 'back' + str(i), tmp, m.__dict__[outp])
class Nesting03: def __init__(self): self.sub1 = Submodule(2) self.sub2 = Submodule(3) self.append_worker(self.worker) self.start = Port(bool, 'in', init=False) self.result = Port(bool, 'out', init=False, protocol='valid') def worker(self): wait_value(True, self.start) self.sub1.i.wr(10) self.sub2.i.wr(20) clksleep(10) result1 = self.sub1.o.rd() == 20 result2 = self.sub2.o.rd() == 60 self.result.wr(result1 and result2)
class io03: def __init__(self, x): d = [x] * 10 self.p = Port(bool, 'any', init=d[0]) self.append_worker(self.w) def w(self): d = self.p.rd()
class UartBridge: def __init__(self): self.rx_data = Port(bit8, 'in') self.rx_ready = Port(bit, 'in') self.rx_idle = Port(bit, 'in') self.tx_start = Port(bit, 'out', 0) self.tx_data = Port(bit8, 'out', 0) self.tx_busy = Port(bit, 'in') def tx_char(self, char_c): wait_value(0, self.tx_busy) self.tx_data.wr(char_c) self.tx_start.wr(1) clkfence() wait_value(1, self.tx_busy) self.tx_start.wr(0) def flush_tx(self): wait_value(0, self.tx_busy) def rx_char(self): wait_value(1, self.rx_ready) data: bit8 = self.rx_data.rd() return data
class io_read_conflict03: def __init__(self): self.p = Port(int, 'in', protocol='valid') self.append_worker(self.w) self.append_worker(self.w) def w(self): data = self.p.rd() print(data)
def __init__(self): self.idata = Port(int, 'in') self.ivalid = Port(bool, 'in') self.odata = Port(int, 'out') self.ovalid = Port(bool, 'out') t0 = Port(int, 'any') t0valid = Port(bool, 'any') t1 = Port(int, 'any') t1valid = Port(bool, 'any') self.append_worker(pow, self.idata, self.ivalid, t0, t0valid) self.append_worker(pow, t0, t0valid, t1, t1valid) self.append_worker(pow, t1, t1valid, self.odata, self.ovalid)
def __init__(self): self.i1 = Port(int8, 'in', init=0, protocol='ready_valid') self.i2 = Port(int8, 'in', init=0, protocol='ready_valid') self.o1 = Port(int8, 'out', init=0, protocol='ready_valid') self.o2 = Port(int8, 'out', init=0, protocol='ready_valid') t0_0 = Port(int8, 'any', init=0, protocol='ready_valid') t0_1 = Port(int8, 'any', init=0, protocol='ready_valid') t1_0 = Port(int8, 'any', init=0, protocol='ready_valid') t1_1 = Port(int8, 'any', init=0, protocol='ready_valid') self.append_worker(worker, self.i1, self.i2, t0_0, t0_1, 1) self.append_worker(worker, t0_0, t0_1, t1_0, t1_1, 2) self.append_worker(worker, t1_0, t1_1, self.o1, self.o2, 3)
def __init__(self, start_addr, end_addr): # define i/o self.dout = Port(int8, 'out', protocol='ready_valid') # define internals instq = Queue(uint16, 'any', maxsize=2) opeq = Queue(uint8, 'any', maxsize=2) valueq = Queue(uint8, 'any', maxsize=2) self.append_worker(fetch, start_addr, end_addr, instq) self.append_worker(decode, instq, opeq, valueq) self.append_worker(execute, opeq, valueq, self.dout)