def main(self):
#print('main')
while is_worker_running():
wait_rising(self.clk1)
wait_rising(self.clk2)
msg('rising', self.clk1(), self.clk2())
self.out1.wr(1)
def main(self, out1, out2, out3):
i = 0
while is_worker_running():
out1.wr(i)
out2.wr(i)
out3.wr(i)
i += 1
def main(self, in_q, out1_q, out2_q):
while is_worker_running():
d = in_q.rd()
if d == 0:
out1_q.wr(d)
else:
out2_q.wr(d)
def decode(instq, opeq, valueq):
while polyphony.is_worker_running():
inst = instq.rd()
op = (inst & 0xFF00) >> 8
v = (inst & 0x00FF)
opeq.wr(op)
valueq.wr(v)
def worker(self):
self.status_port.wr(0)
data: bit32 = 0
while is_worker_running():
while True:
cmd: bit32 = self.cmd_in.rd()
if cmd != IO_CMD_NOP:
self.status_port.wr(STATUS_BUSY_FLAG)
break
if cmd == IO_CMD_TX_UART:
data = self.uart_data_in.rd()
self.uart_bridge.tx_char(data & 0xFF)
elif cmd == IO_CMD_RX_UART:
data = self.uart_bridge.rx_char()
self.uart_data_out.wr(data & 0xFF)
elif cmd == IO_CMD_TX_FLUSH_UART:
self.uart_bridge.flush_tx()
data = IO_CMD_REPLY_FLAG | cmd
self.cmd_reply.wr(data)
self.status_port.wr(0)
while True:
cmd = self.cmd_in.rd()
if cmd == IO_CMD_NOP:
break
data = IO_CMD_REPLY_FLAG | IO_CMD_NOP
self.cmd_reply.wr(data)
def other_main(clk1, clk2, out):
print('other_main')
while is_worker_running():
wait_falling(clk1)
wait_falling(clk2)
msg('falling', clk1(), clk2())
out.wr(1)
def life_worker(self, i_bit4, o_bit):
bit3_to_n = [0, 1, 1, 2, 1, 2, 2, 3]
bit3_to_m = [0, 1, 0, 1, 1, 2, 1, 2]
n_to_o = [0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
mat = [0] * 3 #
while polyphony.is_worker_running():
v = i_bit4()
#print("mat", mat)
#print("v", v)
if v == 8:
mat2_old = mat[2]
mat[0] = 0
mat[1] = 0
mat[2] = 0
else:
v0 = bit3_to_n[v]
v1 = bit3_to_m[v]
mat0_old = mat[0]
mat1_old = mat[1]
mat2_old = mat[2]
mat[0] = 16 + v0
mat[1] = mat0_old + v1
mat[2] = mat1_old + v0
#print("mat2_old:", mat2_old)
if (mat2_old & 16) == 16:
out_v = n_to_o[mat2_old & 15]
o_bit.wr(out_v)
def worker(self):
self.cs_n.wr(1)
self.sclk.wr(0)
clksleep(1)
self.write_data(0x20, 0x7F)
while polyphony.is_worker_running():
clksleep(20)
self.write_data(0x20, 0x7F)
clksleep(10)
data_who_am_i = self.read_data(0x0F)
clksleep(10)
data_x_l = self.read_data(0x29)
clksleep(10)
data_y_l = self.read_data(0x2B)
clksleep(10)
data_z_l = self.read_data(0x2D)
clksleep(10)
self.x_led.wr(1 if data_x_l > 0x30 else 0)
self.y_led.wr(1 if data_y_l > 0x30 else 0)
self.z_led.wr(1 if data_z_l > 0x30 else 0)
data_xyz = (data_x_l << 16) | (data_y_l << 8) | data_z_l
self.data24.wr(data_xyz)
def main(self):
while is_worker_running():
if not self.in_cmd.empty():
cmd = self.in_cmd.rd()
ret = self.calc(cmd)
if not self.out_q.full():
self.out_q.wr(ret)
def main(self):
while polyphony.is_worker_running():
self.convst_n.wr(1)
self.cs_n.wr(1)
self.data_ready.wr(0)
clkfence()
self.convst_n.wr(0)
clksleep(CONVST_PULSE_CYCLE)
self.convst_n.wr(1)
clksleep(CONVERSION_CYCLE)
# starting ADC I/O
self.cs_n.wr(0)
sdo_tmp = 0
clksleep(1)
for i in range(16):
self.sclk.wr(0)
sdi_tmp = 1 if (self.din() & (1 << (15 - i))) else 0
self.sdi.wr(sdi_tmp)
clksleep(1)
self.sclk.wr(1)
sdo_tmp = sdo_tmp << 1 | self.sdo.rd()
self.sclk.wr(0)
self.dout.wr(sdo_tmp & 0x0fff)
self.chout.wr((sdo_tmp & 0x7000) >> 12)
self.cs_n.wr(1)
clkfence()
self.data_ready.wr(1)
def w(self, o1_q, o2_q):
i = 0
data = (1, 2, 3, 4, 5)
while is_worker_running():
d = data[i % 5]
i += 1
o1_q.wr(d)
o2_q.wr(i)
def pow(idata, ivalid, odata, ovalid):
while is_worker_running():
wait_rising(ivalid)
d = idata.rd()
odata.wr(d * d)
clkfence()
ovalid.wr(True)
ovalid.wr(False)
def process_sha256(self):
work = [0] * 64 # type: List[bit32]
_h = [0] * 8 # type: List[bit32]
__h = [0] * 8 # type: List[bit32]
while is_worker_running():
v512 = bit32x8_bit512(_h)
self.data_out.wr(v512)
def main(self):
while is_worker_running():
with rule(scheduling='parallel'):
t1 = self.i1.rd()
t2 = self.i2.rd()
t3 = self.i3.rd()
self.o1.wr(t1 * t1)
self.o2.wr(t2 * t2)
self.o3.wr(t3 * t3)
def sin_wave_worker(self, o_port, o_pulse):
v = 0
while polyphony.is_worker_running():
o_port(v)
o_pulse.wr(1)
print("o_pulse:", 1)
o_pulse.wr(0)
clksleep(1)
v = v + 1
def worker(self, width, height, blank_size):
buf0: List[int12] = [255] * (width + blank_size)
buf1: List[int12] = [255] * (width + blank_size)
buf2: List[int12] = [255] * (width + blank_size)
line0 = buf0
line1 = buf1
line2 = buf2
phase = 0
y = blank_size
r0: int12 = 255
r1: int12 = 255
r2: int12 = 255
r3: int12 = 255
r4: int12 = 255
r5: int12 = 255
r6: int12 = 255
r7: int12 = 255
r8: int12 = 255
while is_worker_running():
for x in pipelined(range(blank_size, width + blank_size)):
#for x in range(blank_size, width + blank_size):
d2 = self.inq.rd()
line2[x] = d2
d1 = line1[x]
d0 = line0[x]
r0, r1, r2 = r1, r2, d0
r3, r4, r5 = r4, r5, d1
r6, r7, r8 = r7, r8, d2
out_h = filter3x3(r0, r1, r2, r3, r4, r5, r6, r7, r8, K_H)
out_v = filter3x3(r0, r1, r2, r3, r4, r5, r6, r7, r8, K_V)
#out_h_c = clip(128 + out_h)
#out_v_c = clip(128 + out_v)
out_c = clip(abs(out_h) + abs(out_v) >> 1)
#self.outhq.wr(out_h_c)
#self.outvq.wr(out_v_c)
self.outq.wr(out_c)
phase = (phase + 1) % 3
if phase == 0:
line0 = buf0
line1 = buf1
line2 = buf2
elif phase == 1:
line0 = buf1
line1 = buf2
line2 = buf0
else:
line0 = buf2
line1 = buf0
line2 = buf1
r0 = r1 = r2 = 255
r3 = r4 = r5 = 255
r6 = r7 = r8 = 255
y += 1
if y == height + blank_size:
# TODO:
break
def dac_ds_worker(self, i_port, i_detect, o_data):
while polyphony.is_worker_running():
print("dac_ds_worker")
enable = i_detect.rd()
#print("dac_ds_worker:enable:", enable)
while (enable == 0):
enable = i_detect.rd()
v = i_port()
o_data(v)
print("v:", v)
def worker(self):
while polyphony.is_worker_running():
self.cs_n.wr(1)
self.sclk.wr(0)
clksleep(1)
data: uint16 = self.read_data()
clksleep(1)
self.data16.wr(data)
def compare(self, i1, i2, o1, o2, di):
while is_worker_running():
d1 = i1.rd()
d2 = i2.rd()
if (d1 < d2) == di:
o1.wr(d1)
o2.wr(d2)
else:
o1.wr(d2)
o2.wr(d1)
def mul(factor, data_size, i_q, o_q):
while is_worker_running():
data = [None] * data_size
for i in range(data_size):
data[i] = i_q.rd()
for i in range(data_size):
data[i] *= factor
for i in range(data_size):
o_q.wr(data[i])
def w(self):
while is_worker_running():
while True:
d = self.i.rd()
assert d == 0
d = self.i.rd()
assert d == 1
d = self.i.rd()
assert d == 2
while True:
d = self.i.rd()
def main(self):
self.start(True)
while is_worker_running():
self.out_valid(False)
wait_value(True, self.in_valid)
i = self.in0()
self.out0(i * i)
clkfence()
self.out_valid(True)
break
def main(self):
while is_worker_running():
mode = self.mode.rd()
ret = 0
if mode == 0:
ret = self.read(self.a, self.b)
elif mode == 1:
ret = self.read(self.b, self.c)
elif mode == 2:
pass
else:
ret = self.read(self.c, self.a)
self.result.wr(ret)
def proc(self):
a0: uint18 = 0
a1: uint18 = 0
a2: uint18 = 0
a3: uint18 = 0
while is_worker_running():
self.q.wr(a0 >> 2)
data: uint16 = self.din.rd()
a0 = a1 + data
a1 = a2 + data
a2 = a3 + data
a3 = data
def main(self):
self.start(1)
while is_worker_running():
self.out_valid(0)
# We have to wait the input data ...
wait_value(1, self.in_valid)
i = self.in0()
self.out0(i * i)
# clkfence() function guarantees that the writing to out_valid is executed in a next cycle
clkfence()
self.out_valid(1)
break
def sin_wave_worker(self, o_port, o_pulse):
i = 0
f = 0
while polyphony.is_worker_running():
v = table[i]
clkfence()
o_port(v)
o_pulse(1)
o_pulse(0)
#print(i, ":", v)
if i == (SIN_CYCLE-1):
i = 0
else:
i = i + 1
def dac_ds_worker(self, use_sin_table, i_port, o_port):
i = 0
ti = 0
while polyphony.is_worker_running():
if use_sin_table:
v = table[ti]
if ti == (SIN_CYCLE - 1):
ti = 0
else:
ti = ti + 1
else:
#wait_value(1, self.i_detect)
v = self.i_port.rd()
self.o_port(v)
def xorshift_worker(self, seed, i_start, o_data):
y: bit32 = seed
while polyphony.is_worker_running():
while (1):
flag = i_start.rd()
if flag == 1:
break
y = y ^ (y << 13)
y &= 0xFFFFFFFF
y = y ^ (y >> 17)
y &= 0xFFFFFFFF
y = y ^ (y << 5)
y &= 0xFFFFFFFF
rv = y
for i in range(32):
b: bit = rv & 1
o_data.wr(b)
rv = rv >> 1
def execute(opeq, valueq, dout):
reg0 = 0
reg1 = 0
while polyphony.is_worker_running():
op = opeq.rd()
v = valueq.rd()
if op == MiniVM.LOAD0:
reg0 = v
elif op == MiniVM.LOAD1:
reg1 = v
elif op == MiniVM.ADD:
reg0 = reg0 + reg1
elif op == MiniVM.SUB:
reg0 = reg0 - reg1
elif op == MiniVM.MUL:
reg0 = reg0 * reg1
elif op == MiniVM.HALT:
dout.wr(reg0)
break
def fetch(start_addr, end_addr, instq):
pc = start_addr
program = [
0x0001,
0x0102,
0x0200,
0x0103,
0x0200,
0xFF00, # 1 + 2 + 3
0x0002,
0x0103,
0x0400,
0x0104,
0x0400,
0xFF00
] # 2 * 3 * 4
while polyphony.is_worker_running():
if end_addr < pc:
break
instruction = program[pc]
pc += 1
instq.wr(instruction)
