def _behavior(self):
'''
Implements the behavior of the converter block.
'''
if self.busInport.ready():
trans = self.busInport.read()
op = int(trans.op.value)
if op == OP_WRITE:
self.ramOutport.write(data=Transaction(addr=int(trans.addr),
data=int(trans.data),
be=int(trans.be)))
elif op == OP_READ:
self.ramOutport.write(data=Transaction(addr=int(trans.addr),
be=int(trans.be)),
execute_behavior=True)
assert (self.ramInport.ready())
data = self.ramInport.read()
self.busOutport.write(
data=Transaction(addr=int(trans.data),
data=data,
be=int((1 << self.__bpd) - 1),
op=OP_WRITE))
else:
raise ValueError("op of value {} isn't defined.".format(op))
def test(te):
# Determine the parameters of the test.
getval = lambda w: randint(0, (1 << w) - 1)
width = te.c.d.W
init = te.c.d.INIT
total = 1 << width
incx = getval(4)
incitrs = randint(1, total)
decx = -getval(4)
decitrs = randint(1, total)
itrs = incitrs + decitrs
# Determine the expected results.
incexp = [(val * incx + init) % total for val in range(incitrs)]
decinit = incexp[-1]
decexp = [((val + 1) * decx + decinit) % total
for val in range(decitrs)]
exp = list(
) # The initial value will be registered twice, so it's expected!
exp.extend(incexp)
exp.extend(decexp)
#for val in exp: te.log.info("exp: {:x}".format(val))
# Determine the actual transactions.
incact = [Transaction(dx=incx, adv=1) for _ in range(incitrs - 1)]
decact = [Transaction(dx=decx, adv=1) for _ in range(decitrs + 1)]
act = list()
act.extend(incact)
act.extend(decact)
# Write out the transaction
for trans in act:
te.c.d.append(trans)
# Wait until the appropriate amount of cycles have passed.
yield te.c.d.cycle(itrs + 1)
# Compare results
for idx, ex in enumerate(exp):
ac = te.c.m[idx]
te.log.info("Actual: <{}>, Expected: <{}>...".format(ac, ex))
if ac != ex:
te.log.error("Test failed!")
raise ReturnValue(False)
te.log.info("Test successful...")
raise ReturnValue(True)
def test_basic(dut):
'''
Simply write random values into the crossbar buses.
It's critical the yield Timer is set to wait long enough until
all the data passes through!
'''
te = yield perform_setup(dut)
rword = lambda: randint(0, (1 << 32) - 1)
writes = 512
# Simply write a bunch of random data with random addresses into
# the writing interfaces of the crossbar.
for each_write in range(writes):
for each_bus in range(te.buses):
for each_source in range(te.inputs(each_bus)):
source = te.sources(bus=each_bus, idx=each_source)
source.write(data=Transaction(addr=rword(), data=rword()))
# This wait needs to be long enough to ensure all the data has
# passed through the crossbar.
yield Timer(16, "us")
# Initiate the comparison with the scoreboard. Comparisons are
# completed with sets since currently the reading interfaces have
# no way on knowing where their data came from.
for each_bus in range(te.buses):
for each_set in range(te.outputs(each_bus)):
te.gathers(bus=each_bus, idx=each_set, exp_act="exp").perform()
te.gathers(bus=each_bus, idx=each_set, exp_act="act").perform()
def test_backpressure(dut):
'''
Verify the swiss fifo's ability to handle being completely filled, and
then emptied.
'''
# Generate the testbench environment.
total = 128
max_value = (1 << 32) - 1
te = yield perform_setup(dut, total)
# Disable the reading interface.
te.setrdallow(NeverAllow)
# Write out the data.
for _ in range(total):
te.source.write(data=Transaction(data=randint(0, max_value)))
# Wait until the write ready is de-asserted.
yield Timer(1, "us")
# Allow the data to pass through.
te.setrdallow(CoinTossAllow)
# If something goes wrong, this test can timeout.
yield Timer(1000, "us")
te.log.info("Timed out!")
raise TestFailure()
def test_sequential(dut):
'''
Simply writes data sequentially into the flip flop
and checks for the correct output.
'''
# Prepare test environment.
te = yield perform_setup(dut)
width = te.p.d.W
stages = te.p.d.S
total = 1<<width
te.log.info("Total transactions <{}>, total stages <{}>...".format(total,stages))
# Perform the test.
te.log.info("Performing the test...")
# Write out the randomly generated values.
ds = [randint(0,total-1) for _ in range(total)]
for d in ds: te.p.d.append(transaction=Transaction(d=d,vld=1))
# Wait until all the stages has been collected by the monitor.
for _ in range(total+stages): yield te.p.d.cycle()
# Verify the results.
for idx, d in enumerate(ds):
q = te.p.m[idx+stages]
te.log.info("Wrote <{}>, Read <{}>...".format(d,q))
if d!=q: raise TestFailure()
te.log.info("Test completed successfully...")
raise TestSuccess()
def BinaryToInt(trans):
'''
Converts a transaction of
binary values into a new transaction
of integers.
'''
return Transaction(addr=int(trans.addr), data=int(trans.data))
def test(te):
# Gather important data.
width = te.c.d.W
aval = te.c.d.X
init = te.c.d.INIT
total = 1 << width
itrs = [4, 3, 2, 3, 3, 6, 5]
for _ in range(itrs[0]):
te.c.d.append(Transaction(adv=1))
for _ in range(itrs[1]):
te.c.d.append(Transaction(adv=1, clr=1))
for _ in range(itrs[2]):
te.c.d.append(Transaction(adv=1, clr=0))
for _ in range(itrs[3]):
te.c.d.append(Transaction(adv=0, clr=0))
for _ in range(itrs[4]):
te.c.d.append(Transaction(ld=0, nval=randint(0, total - 1)))
for _ in range(itrs[5]):
te.c.d.append(Transaction(ld=1, nval=randint(0, total - 1)))
for _ in range(itrs[6]):
te.c.d.append(Transaction(adv=1))
yield te.c.d.cycle(amount=sum(itrs))
raise ReturnValue(True)
def ChangeWidth(trans, aw, dw):
'''
Creates a new transaction whose
address and data fields are masked
according to the specified widths.
'''
awm = (1 << aw) - 1
dwm = (1 << dw) - 1
return Transaction(addr=trans.addr & awm, data=trans.data & dwm)
def _up_func(self, trans):
self.__buff.append(trans.data)
if len(self.__buff) == self.__mult:
mask = (1 << self.__width) - 1
res = 0
for each, data in enumerate(self.__buff):
res |= (int(data) & mask) << (self.__width * each)
self.__buff = []
return Transaction(data=BinaryValue(
value=res, bits=(self.__width * self.__mult), bigEndian=False))
def write(self, addr, data, be=None, op=OP_WRITE):
'''
Writes data over the bus interface. addr refers to the destination
address. data is the specified data. be is the byte enable mask. op
is the operation, which, by default is write.
'''
if be is None:
beWidth = len(self._drivers.wr._interface.be)
be = int(((1 << beWidth) - 1))
self._drivers.wr.write(
data=Transaction(addr=addr, data=data, be=be, op=op))
def _behavior(self):
if self.__inport.ready():
trans = self.__inport.read()
wrdata = int(trans.data)
for each in range(self.__mult):
mask = (1 << self.__width) - 1
shift = each * self.__width
rdata = (wrdata & (mask << shift)) >> shift
self.__outport.write(
Transaction(data=BinaryValue(
value=rdata, bits=self.__width, bigEndian=False)))
def test_valid(dut):
'''
Checks to see if the valid flag is working properly.
'''
# Prepare test environment.
te = yield perform_setup(dut)
total = 1<<te.width
for d in range(total): te.srcblk.write(data=Transaction(d=d,vld=randint(0,1)))
for _ in range(total): yield te.wait()
def test_sequential(dut):
'''
Simply writes data sequentially into the flip flop
and checks for the correct output.
'''
# Prepare test environment.
te = yield perform_setup(dut)
total = 1<<te.width
for d in range(total): te.srcblk.write(data=Transaction(d=d,vld=0x1))
for _ in range(total): yield te.wait()
def test_random(dut):
'''
Verifies the flip flop with random data. This test
also ensures a clock cycle isn't wasted between
transactions.
'''
# Prepare test environment.
te = yield perform_setup(dut)
total = 1<<te.width
for d in range(total): te.srcblk.write(data=Transaction(d=randint(0,total-1),vld=randint(0,1)))
for _ in range(total): yield te.wait()
def test_basic(dut):
'''
Simply write random values into the swiss fifos.
'''
# Generate the testbench environment.
total = 128
max_value = (1 << 32) - 1
te = yield perform_setup(dut, total)
# Write out the data.
for _ in range(total):
te.source.write(data=Transaction(data=randint(0, max_value)))
# If something goes wrong, this test can timeout.
yield Timer(1000, "us")
te.log.info("Timed out!")
raise TestFailure()
def test_congestion(dut):
'''
Effectively performs the same operations as test_basic, however
congestion is simulated.
THERE'S ACTUALLY A FUNDAMENTAL PROBLEM WITH THIS TEST. Take note
of the yield Timer that separates the data injection and the comparison.
Due to the random nature of the test, there's a chance that the amount of
time needed to inject the data and for that data to pass through the interconnect
could be greater than the wait. If this happens, the comparison will trigger
prematurely and fail.
SO, at some point, this will need to be fixed... xD
'''
te = yield perform_setup(dut)
rword = lambda: randint(0, (1 << 32) - 1)
writes = 256
# Configure the allows of the reading interfaces.
for each_bus in range(te.buses):
for each_output in range(te.outputs(each_bus)):
te.drivers(bus=each_bus, idx=each_output,
wr_rd="rd").allow = CoinTossAllow
# Welp, the following is just a copy and paste of test_basic.
for each_write in range(writes):
for each_bus in range(te.buses):
for each_source in range(te.inputs(each_bus)):
source = te.sources(bus=each_bus, idx=each_source)
source.write(data=Transaction(addr=rword(), data=rword()))
# This wait needs to be long enough to ensure all the data has
# passed through the crossbar.
yield Timer(16, "us")
# Initiate the comparison with the scoreboard. Comparisons are
# completed with sets since currently the reading interfaces have
# no way on knowing where their data came from.
for each_bus in range(te.buses):
for each_set in range(te.outputs(each_bus)):
te.gathers(bus=each_bus, idx=each_set, exp_act="exp").perform()
te.gathers(bus=each_bus, idx=each_set, exp_act="act").perform()
def test_basic(dut):
'''
Simply writes out data into the afifo.
'''
# Generate the testbench environment.
te = yield perform_setup(dut)
# Generate the parameters of the test.
max_value = (1<<te.width)-1
te.cntns.total = 256
# Write out the data.
for _ in range(te.cntns.total): te.source.write(data=Transaction(data=randint(0,max_value)))
# If something goes wrong, this test can timeout.
yield Timer(1000, "us")
te.log.info("Timed out!")
raise TestFailure()
def test_gray(dut):
te = yield perform_setup(dut)
width = te.cd.W
total = 1 << width
itrs = total * 8
edly = 1
ddly = 2
te.cd.append(Transaction(adv=1))
yield te.cd.cycle(amount=itrs)
for i in range(len(te.cm) - ddly):
cntr = te.cm[i]
en = te.em[i + edly]
de = te.dm[i + ddly]
te.log.info("Cntr: {}, En: {}, De: {}".format(cntr, en, de))
if cntr != de: raise TestFailure()
raise TestSuccess()
def test_congestion(dut):
'''
Writes out data into the afifo, however
congestion is simulated.
'''
# Generate the testbench environment.
te = yield perform_setup(dut)
# Generate the parameters of the test.
max_value = (1<<te.width)-1
te.cntns.total = 256
te.setwrallow(CoinTossAllow)
te.setrdallow(CoinTossAllow)
# Write out the data.
for _ in range(te.cntns.total): te.source.write(data=Transaction(data=randint(0,max_value)))
# If something goes wrong, this test can timeout.
yield Timer(1000, "us")
te.log.info("Timed out!")
raise TestFailure()
def test_sequential(dut):
'''
Simply writes data sequentially into the flip flop syncrhonizer
and checks for the correct output.
***This test isn't really thought out. A better should eventually
be created instead.
'''
# Prepare the test environment.
te = yield perform_setup(dut)
width = te.ffsd.W
total = 1 << width
te.log.info("Total transactions <{}>...".format(total))
# Perform the test.
te.log.info("Performing the test...")
te.log.info("Writing out the non-zero, sequential data...")
ds = [value + 1 for value in range(total - 1)]
for d in ds:
te.ffsd.append(transaction=Transaction(d=d, vld=1))
prev_q = 0
q = 0
for d in ds:
# Keep reading until a different value is seen.
while prev_q == q:
q = yield te.ffsd.read()
te.log.info("D=<{}>, Q=<{}>...".format(d, q))
if d != q: raise TestFailure()
prev_q = q
te.log.info("Test completed successfully...")
raise TestSuccess()
def test(te):
# Specify important data.
itrs = 64
init = te.e.d.INIT
width = te.e.d.W
valen = te.e.d.EVLD
hpen = int(te.dut.EHP.value)
hnen = int(te.dut.EHN.value)
getval = lambda w: randint(0, (1 << w) - 1)
# Randomly generate the input transactions.
in_trans = [
Transaction(d=getval(width), vld=getval(1)) for _ in range(itrs)
]
# Generate the expected output.
out_vals = getexp(in_trans, init, valen, hpen, hnen)
#for val in out_vals: te.log.info("out val: {:x}".format(val))
# Write out the transactions.
for trans in in_trans:
te.e.d.append(trans)
# Wait until all transactions have been written out.
yield te.e.d.cycle(amount=itrs + 1)
# Compare actual output values with expected.
for idx, exp in enumerate(out_vals):
act = te.e.m[idx]
te.log.info("Actual: <{:x}>, Expected: <{:x}>...".format(act, exp))
if act != exp:
te.log.error("Test failed!")
raise ReturnValue(False)
te.log.info("Test successful...")
raise ReturnValue(True)
class TestEnvironment(object):
'''
Defines the test environment.
'''
def __init__(self,
dut,
wrStartAllow=AlwaysAllow,
rdStartAllow=AlwaysAllow):
'''
Constructor. dut is the device-under-test that consists of all the cocotb
SimHandles.
'''
# Create the agents and models.
DUT_TOTAL = int(dut.DUT_TOTAL.value)
wrdrvs = []
rddrvs = []
rdmons = []
modelblks = []
scoreblks = []
clkintrs = {}
clkparams = {}
rstintrs = {}
rstparams = {}
for eachDut in range(DUT_TOTAL):
# Acquire useful values.
specificDut = getattr(dut, "dut{}".format(eachDut))
EASYNC = int(specificDut.EASYNC.value)
wrPeriod = (randint(3, 10), "ns")
rdPeriod = wrPeriod if EASYNC == 0 else (randint(3, 10), "ns")
W = int(specificDut.W.value)
MULT = int(specificDut.MULT.value)
# Collect system parameters.
clkintrs["wrclk{}".format(eachDut)] = specificDut.wrclk
clkintrs["rdclk{}".format(eachDut)] = specificDut.rdclk
clkparams["wrclk{}".format(eachDut)] = Namespace(period=wrPeriod)
clkparams["rdclk{}".format(eachDut)] = Namespace(period=rdPeriod)
rstintrs["wrrst{}".format(eachDut)] = specificDut.wrrst
rstintrs["rdrst{}".format(eachDut)] = specificDut.rdrst
rstparams["wrrst{}".format(eachDut)] = Namespace(
active_mode=1,
associated_clock=specificDut.wrclk,
wait_cycles=32)
rstparams["rdrst{}".format(eachDut)] = Namespace(
active_mode=1,
associated_clock=specificDut.rdclk,
wait_cycles=32)
# Create the agents.
wrdrv = HandshakeWriteDriver(interface=HandshakeInterface(
data=specificDut.wrdata,
vld=specificDut.wrvld,
rdy=specificDut.wrrdy,
clk=specificDut.wrclk,
rst=specificDut.wrrst),
allow=wrStartAllow)
rddrv = HandshakeReadDriver(interface=HandshakeInterface(
data=specificDut.rddata,
vld=specificDut.rdvld,
rdy=specificDut.rdrdy,
clk=specificDut.rdclk,
rst=specificDut.rdrst),
allow=rdStartAllow)
rdmon = HandshakeMonitor(interface=rddrv._interface)
# Create the blocks.
modelblk = UpFifoModel(width=W, mult=MULT)
scoreblk = ScoreBlock(name="score.dut{}".format(eachDut))
# Store blocks.
wrdrvs.append(wrdrv)
rddrvs.append(rddrv)
rdmons.append(rdmon)
scoreblks.append(scoreblk)
modelblks.append(modelblk)
# Create the system agents.
clkdrv = ClockDriver(interface=Interface(**clkintrs),
param_namespace=Namespace(**clkparams))
rstdrv = ResetDriver(interface=Interface(**rstintrs),
param_namespace=Namespace(**rstparams))
# Create the blocks.
sourceblk = SourceBlock()
assertblk = AssertBlock(inputs=DUT_TOTAL)
# Perform the connections.
for eachDut, (wrdrv, modelblk, rdmon, scoreblk) in enumerate(
zip(wrdrvs, modelblks, rdmons, scoreblks)):
sourceblk.outport.connect(wrdrv.inport)
sourceblk.outport.connect(modelblk.inport)
rdmon.outport.connect(scoreblk.inports(0))
modelblk.outport.connect(scoreblk.inports(1))
scoreblk.outport.connect(assertblk.inports(eachDut))
self.__dut = dut
self.__rstdrv = rstdrv
self.__wrdrvs = wrdrvs
self.__rddrvs = rddrvs
self.__sourceblk = sourceblk
self.__log = SimLog("cocotb.te")
log = property(lambda self: self.__log)
DUT_TOTAL = property(lambda self: int(self.__dut.DUT_TOTAL.value))
W = property(lambda self: int(self.__dut.W.value))
write = lambda self, data: self.__sourceblk.write(data=Transaction(data=
data))
setWrAllow = lambda self, allow: [
setattr(drv, "allow", allow) for drv in self.__wrdrvs
]
setRdAllow = lambda self, allow: [
setattr(drv, "allow", allow) for drv in self.__rddrvs
]
@coroutine
def start(self):
'''
Starts the test by causing the test to delay until the resets are inactive.
'''
yield self.__rstdrv.wait()
class TestEnvironment(object):
'''
Defines the test environment.
'''
def __init__(self, dut):
'''
Constructor. dut is the device-under-test that consists of all the cocotb
SimHandles.
'''
self.__rstDrvs = []
self.__log = SimLog("cocotb.log")
#---------------------------------------------------------------------#
# Configure ipmaxi_full_inst
ipmaxiFullInst = dut.ipmaxi_full_inst
# Create the agents and blocks...
ClockDriver(interface=Interface(clk=ipmaxiFullInst.clk),
param_namespace=Namespace(clk=Namespace(period=(10,
"ns"))),
name="ipmaxiFullInst")
rstDrv = ResetDriver(interface=Interface(rst=ipmaxiFullInst.rst),
param_namespace=Namespace(
active_mode=1,
associated_clock=ipmaxiFullInst.clk,
wait_cycles=32))
self.__rstDrvs.append(rstDrv)
busAgts = []
respMons = []
respScrBlks = []
TOTAL_CCTBPLBS = int(ipmaxiFullInst.TOTAL_CCTBPLBS.value)
B_AW = int(ipmaxiFullInst.B_AW.value)
for eachBusAgt in range(TOTAL_CCTBPLBS):
baseAddr = (int(ipmaxiFullInst.B_BASES.value) >>
(eachBusAgt * B_AW)) & ((1 << B_AW) - 1)
busAgt = BusAgent(baseAddr=baseAddr,
wrInterface=HandshakeInterface(
addr=ipmaxiFullInst.wraddr[eachBusAgt],
data=ipmaxiFullInst.wrdata[eachBusAgt],
be=ipmaxiFullInst.wrbe[eachBusAgt],
op=ipmaxiFullInst.wrop[eachBusAgt],
vld=ipmaxiFullInst.wrvld[eachBusAgt],
rdy=ipmaxiFullInst.wrrdy[eachBusAgt],
clk=ipmaxiFullInst.clk,
rst=ipmaxiFullInst.rst),
rdInterface=HandshakeInterface(
addr=ipmaxiFullInst.rdaddr[eachBusAgt],
data=ipmaxiFullInst.rddata[eachBusAgt],
be=ipmaxiFullInst.rdbe[eachBusAgt],
op=ipmaxiFullInst.rdop[eachBusAgt],
vld=ipmaxiFullInst.rdvld[eachBusAgt],
rdy=ipmaxiFullInst.rdrdy[eachBusAgt],
clk=ipmaxiFullInst.clk,
rst=ipmaxiFullInst.rst))
respMon = HandshakeMonitor(interface=HandshakeInterface(
resp=ipmaxiFullInst.respresp[eachBusAgt],
op=ipmaxiFullInst.respop[eachBusAgt],
vld=ipmaxiFullInst.respvld[eachBusAgt],
rdy=ipmaxiFullInst.resprdy[eachBusAgt],
clk=ipmaxiFullInst.clk,
rst=ipmaxiFullInst.rst))
respScrBlk = ScoreBlock(name="resp{}".format(eachBusAgt))
busAgts.append(busAgt)
respMons.append(respMon)
respScrBlks.append(respScrBlk)
respScrBlk = ScoreBlock(name="resp")
busScrBlk = ScoreBlock(name="bus")
assertBlk = AssertBlock()
# Peform the connections...
for respMon, respScrBlk in zip(respMons, respScrBlks):
respMon.outport.connect(
SwissBlock(lambda trans: int(trans.resp.value)).inport
).outport.connect(respScrBlk.inports(0))
respMon.outport.connect(
SwissBlock(lambda trans: 0).inport).outport.connect(
respScrBlk.inports(1))
respScrBlk.outport.connect(assertBlk.inport)
busScrBlk.outport.connect(assertBlk.inport)
# Assign the private members...
self.__ipmaxiFullInstBusAgts = busAgts
self.__ipmaxiFullInstBusScrBlk = busScrBlk
#---------------------------------------------------------------------#
# Configure ipmaxi_wr_inst
ipmaxiWrInst = dut.ipmaxi_wr_inst
ClockDriver(interface=Interface(clk=ipmaxiWrInst.clk),
param_namespace=Namespace(clk=Namespace(period=(10,
"ns"))),
name="ipmaxiWrInst")
rstDrv = ResetDriver(interface=Interface(rst=ipmaxiWrInst.rst),
param_namespace=Namespace(
active_mode=1,
associated_clock=ipmaxiWrInst.clk,
wait_cycles=32))
self.__rstDrvs.append(rstDrv)
wrDrv = HandshakeWriteDriver(
interface=HandshakeInterface(addr=ipmaxiWrInst.wraddr,
data=ipmaxiWrInst.wrdata,
be=ipmaxiWrInst.wrbe,
vld=ipmaxiWrInst.wrvld,
rdy=ipmaxiWrInst.wrrdy,
clk=ipmaxiWrInst.clk,
rst=ipmaxiWrInst.rst))
HandshakeReadDriver(
interface=HandshakeInterface(resp=ipmaxiWrInst.bresp,
vld=ipmaxiWrInst.bvalid,
rdy=ipmaxiWrInst.bready,
clk=ipmaxiWrInst.clk,
rst=ipmaxiWrInst.rst))
self.__ipmaxiWrInstWrDrv = wrDrv
#---------------------------------------------------------------------#
# Configure ipmaxi_rdwr_inst
ipmaxiRdWrInst = dut.ipmaxi_rdwr_inst
ClockDriver(interface=Interface(clk=ipmaxiRdWrInst.clk),
param_namespace=Namespace(clk=Namespace(period=(10,
"ns"))),
name="ipmaxiRdWrInst")
rstDrv = ResetDriver(interface=Interface(rst=ipmaxiRdWrInst.rst),
param_namespace=Namespace(
active_mode=1,
associated_clock=ipmaxiRdWrInst.clk,
wait_cycles=32))
self.__rstDrvs.append(rstDrv)
wrWrDrv = HandshakeWriteDriver(
interface=HandshakeInterface(addr=ipmaxiRdWrInst.wr_wraddr,
data=ipmaxiRdWrInst.wr_wrdata,
be=ipmaxiRdWrInst.wr_wrbe,
vld=ipmaxiRdWrInst.wr_wrvld,
rdy=ipmaxiRdWrInst.wr_wrrdy,
clk=ipmaxiRdWrInst.clk,
rst=ipmaxiRdWrInst.rst))
rdWrDrv = HandshakeWriteDriver(
interface=HandshakeInterface(addr=ipmaxiRdWrInst.rd_wraddr,
data=ipmaxiRdWrInst.rd_wrdata,
vld=ipmaxiRdWrInst.rd_wrvld,
rdy=ipmaxiRdWrInst.rd_wrrdy,
clk=ipmaxiRdWrInst.clk,
rst=ipmaxiRdWrInst.rst))
rdRdDrv = HandshakeReadDriver(
interface=HandshakeInterface(addr=ipmaxiRdWrInst.rd_rdaddr,
data=ipmaxiRdWrInst.rd_rddata,
resp=ipmaxiRdWrInst.rd_rdresp,
vld=ipmaxiRdWrInst.rd_rdvld,
rdy=ipmaxiRdWrInst.rd_rdrdy,
clk=ipmaxiRdWrInst.clk,
rst=ipmaxiRdWrInst.rst))
HandshakeReadDriver(
interface=HandshakeInterface(resp=ipmaxiRdWrInst.bresp,
vld=ipmaxiRdWrInst.bvalid,
rdy=ipmaxiRdWrInst.bready,
clk=ipmaxiRdWrInst.clk,
rst=ipmaxiRdWrInst.rst))
rdRdMon = HandshakeMonitor(interface=rdRdDrv._interface)
rdPrBlk = PrintBlock(name="ipmaxiRdWrInst")
rdRdMon.outport.connect(rdPrBlk.inport)
self.__ipmaxiRdWrInstWrWrDrv = wrWrDrv
self.__ipmaxiRdWrInstRdWrDrv = rdWrDrv
#---------------------------------------------------------------------#
# Configure ipmaxi_single_inst
ipmaxiSingleInst = dut.ipmaxi_single_inst
ClockDriver(interface=Interface(clk=ipmaxiSingleInst.clk),
param_namespace=Namespace(clk=Namespace(period=(10,
"ns"))),
name="ipmaxiSingleInst")
rstDrv = ResetDriver(interface=Interface(rst=ipmaxiSingleInst.rst),
param_namespace=Namespace(
active_mode=1,
associated_clock=ipmaxiSingleInst.clk,
wait_cycles=32))
self.__rstDrvs.append(rstDrv)
busAgt = BusAgent(
baseAddr=0x00000000,
wrInterface=HandshakeInterface(addr=ipmaxiSingleInst.wraddr,
data=ipmaxiSingleInst.wrdata,
be=ipmaxiSingleInst.wrbe,
op=ipmaxiSingleInst.wrop,
vld=ipmaxiSingleInst.wrvld,
rdy=ipmaxiSingleInst.wrrdy,
clk=ipmaxiSingleInst.clk,
rst=ipmaxiSingleInst.rst),
rdInterface=HandshakeInterface(addr=ipmaxiSingleInst.rdaddr,
data=ipmaxiSingleInst.rddata,
be=ipmaxiSingleInst.rdbe,
op=ipmaxiSingleInst.rdop,
vld=ipmaxiSingleInst.rdvld,
rdy=ipmaxiSingleInst.rdrdy,
clk=ipmaxiSingleInst.clk,
rst=ipmaxiSingleInst.rst))
self.__ipmaxiSingleInstBusAgt = busAgt
#---------------------------------------------------------------------#
# Other assignments
self.__dut = dut
log = property(lambda self: self.__log)
ipmaxiWrInstWrite = lambda self, addr, data, be: self.__ipmaxiWrInstWrDrv.write(
Transaction(addr=addr, data=data, be=be))
ipmaxiWrInstBPD = property(
lambda self: int(self.__dut.ipmaxi_wr_inst.B_BPD.value))
ipmaxiRdWrInstWrite = lambda self, addr, data, be: self.__ipmaxiRdWrInstWrWrDrv.write(
Transaction(addr=addr, data=data, be=be))
ipmaxiRdWrInstRead = lambda self, addr, raddr: self.__ipmaxiRdWrInstRdWrDrv.write(
Transaction(addr=addr, data=raddr))
ipmaxiRdWrInstBPD = property(
lambda self: int(self.__dut.ipmaxi_rdwr_inst.B_BPD.value))
ipmaxiSingleInstBusAgt = property(
lambda self: self.__ipmaxiSingleInstBusAgt)
ipmaxiSingleInstBPD = property(
lambda self: int(self.__dut.ipmaxi_single_inst.B_BPD.value))
ipmaxiFullInstBusAgts = lambda self, idx: self.__ipmaxiFullInstBusAgts[idx]
ipmaxiFullInstCompare = lambda self, act, exp: self.__ipmaxiFullInstBusScrBlk.compare(
act, exp)
ipmaxiFullInstBPD = property(
lambda self: int(self.__dut.ipmaxi_full_inst.B_BPD.value))
@coroutine
def start(self):
'''
Waits until all resets are out of reset.
'''
for rstDrv in self.__rstDrvs:
yield rstDrv.wait()
def _reg_func(self, trans):
q = self.__reg
if self.__evld==0 or trans.vld!=0:
self.__reg = trans.d & self.__mask
return Transaction(q=q)