buf_small, buf_big, buf1_name, buf2_name, buf3_name, bufz, tdc_dff, H_stdc = preparations.read_std_cell_names(
platform, track, absGenDir + 'std_cell_names_public.json')
#--------------------------------------------------------
# check for private directory
#--------------------------------------------------------
if outMode == 'macro' or outMode == 'full':
if os.path.isdir(absPvtDir) != 1:
print(
"Error: Need private directory for mode 'macro' or 'full'. Check README"
)
sys.exit(1)
#--------------------------------------------------------
# read the aux-cells
#--------------------------------------------------------
dco_CC_name, dco_FC_name = preparations.aux_copy_export(
dco_flowDir, dco_CC_lib, dco_FC_lib)
preparations.aux_copy_export(pll_flowDir, dco_CC_lib, dco_FC_lib)
W_CC, H_CC, W_FC, H_FC = preparations.aux_parse_size(
dco_CC_lib, dco_FC_lib)
A_CC = W_CC * H_CC
A_FC = W_FC * H_FC
buf_small, buf_big, buf1_name, buf2_name, buf3_name, bufz, tdc_dff, H_stdc = preparations.read_std_cell_names(
platform, track, absPvtDir + 'std_cell_names.json')
else: # dummy areas for verilog mode
A_CC = 0.01
A_FC = 0.01
#--------------------------------------------------------
# read input
#--------------------------------------------------------
print(
p2_rng_s= 0.8
max_r_l=5
aLib = ''
sCell = ''
sLib = ''
num_core=4
#------------------------------------------------------------------------------
# make HSPICE directory tree
#------------------------------------------------------------------------------
hspice=1
finesim=0
preparations.dir_tree(outMode,absPvtDir_plat,outputDir,extDir,calibreRulesDir,hspiceDir,finesimDir,dco_flowDir,pll_flowDir)
preparations.aux_copy_export(dco_flowDir,dco_CC_lib,dco_FC_lib)
#------------------------------------------------------------------------------
# design & test_env sets definition
#------------------------------------------------------------------------------
sys.setrecursionlimit(10000) #expand the recursion limit if exceeded
vm1=txt_mds.varmap()
vm1.get_var('n_cc',8,16,8) #[0]=n_cc
vm1.get_var('n_drv',8,8,8) #[1]=n_drv
vm1.get_var('n_fc',16,32,16) #[2]=n_fc
vm1.get_var('n_stg',8,8,1) #[3]=n_stg
vm1.cal_nbigcy()
vm1.combinate()
vdd=[1.2] #vdd[0] is the nominal val
temp=[25] #tmep[0] is the nominal val