def strRegImmed(
state: programState.ProgramState
) -> Tuple[programState.ProgramState, Union[
programState.RunError, None]]:
adr, err = state.getReg(dest1.contents)
newState: Union[
None, programState.RunError] = state.storeRegister(
adr + value, src.contents, bitSize)
return state, err if newState is None else newState
def strDualReg(
state: programState.ProgramState
) -> Tuple[programState.ProgramState, Union[
programState.RunError, None]]:
adr1, err = state.getReg(dest1.contents)
if err is None:
adr2, err = state.getReg(dest2.contents)
else:
adr2, _ = state.getReg(dest2.contents)
newState: Union[
None, programState.RunError] = state.storeRegister(
adr1 + adr2, src.contents, bitSize)
return state, err if newState is None else newState
def push(state: programState.ProgramState) -> Tuple[programState.ProgramState, Union[programState.RunError, None]]:
if len(regs) == 0:
return state, None
# head, *tail = registers
address = state.getReg("SP")
# check address is in 0...stacksize
if address > (state.getLabelAddress("__STACKSIZE")) or address < 0:
return state, programState.RunError("Stack overflow", programState.RunError.ErrorType.Error)
for reg in regs:
address -= 4
err = state.storeRegister(address, reg, 32)
if err is not None:
return state, err
state.setReg("SP", address)
return state, None
def strDualReg(state: programState.ProgramState) -> Tuple[programState.ProgramState, Union[programState.RunError, None]]:
adr1 = state.getReg(dest1.contents)
adr2 = state.getReg(dest2.contents)
newState: Union[None, programState.RunError] = state.storeRegister(adr1 + adr2, src.contents, bitSize)
return state, newState