def main():
display_logo()
if ehdnsxmgor() != True:
sys.exit()
args = pass_args('Generate a Verilog model representing a DC transfer curve in PWL waveform', 'cfg_txf.py')
if args.ghktdjvn:
print ghktdjvn()
param = read_cfg(args.config)
TxfCurveGenerator(param)
print '=== Generating transfer curve module is completed ==='
def main():
display_logo()
args = pass_args(
'Generate a LUT Verilog model for piecewise linear modeling',
'cfg_lut.py')
if args.ghktdjvn:
print ghktdjvn()
param = read_cfg(args.config)
param.update({'ehdnsxmgorfkdlt': ehdnsxmgor()})
LookUpTablemD(param)
print '=== Generating LUT module is completed ==='
def run(cfg_file): param = read_cfg(cfg_file) c = TxfCurveGenerator(param) freq, meas = sim_ac.run() gaindB = sim_ac.postprocess(freq, meas, sim_ac.get_param()) sim_ac.plot(freq, gaindB, sim_ac.get_param())
def main():
args = pass_args('Print out an analytic equation of a transient response for given s-domain transfer function expression.', 'cfg_tf.py')
cfg = read_cfg(args.config)
equation = Txf2Tran(cfg['numerator'], cfg['denumerator'], cfg['in_type'])
def run(cfg_file):
param = read_cfg(cfg_file)
sim_ac = RunACSimulation(param)
freq, meas = sim_ac.run()
gaindB = sim_ac.postprocess(freq, meas, sim_ac.get_param())
sim_ac.plot(freq, gaindB, sim_ac.get_param())