def test_sub_access_non_vector():
sa = SubAccess(n("vc", uw(8)), u(2, w(3)), uw(8))
assert not check(sa)
sa = SubAccess(n("vc", bdl(a=(vec(uw(8), 10), True))),
u(2, w(3)), vec(uw(8), 10))
assert not check(sa)
def test_sub_index_type_wrong():
vc = vec(uw(8), 10)
si = SubIndex(n("vc", vc), 5, sw(8))
assert not check(si)
vc = vec(vec(uw(8), 10), 20)
si = SubIndex(n("vc", vc), 19, vec(uw(8), 20))
assert not check(si)
def test_memory_basis():
mem = DefMemory("m", vec(uw(8), 10))
assert check(mem)
serialize_stmt_equal(mem, 'cmem m : UInt<8>[10]')
mem = DefMemory("m", vec(bdl(a=(uw(8), False)), 10))
assert check(mem)
serialize_stmt_equal(mem, 'cmem m : {a : UInt<8>}[10]')
def test_sub_access_idx_non_uint():
vc = vec(uw(8), 10)
sa = SubAccess(n("vc", vc), s(2, w(3)), uw(8))
assert not check(sa)
vc = vec(uw(8), 10)
sa = SubAccess(n("vc", vc), n("a", sw(8)), uw(8))
assert not check(sa)
def test_write_port_clock_wrong():
mem_ref = n("m", vec(uw(8), 10))
mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", uw(1)))
assert not check(mw)
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), u(0, w(1)))
assert not check(mw)
def test_read_port_clock_wrong():
mem_ref = n("m", vec(uw(8), 10))
mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", uw(1)))
assert not check(mr)
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), u(0, w(1)))
assert not check(mr)
def test_sub_index_over_bound():
vc = vec(uw(8), 10)
si = SubIndex(n("vc", vc), 10, uw(8))
assert not check(si)
vc = vec(vec(uw(8), 10), 20)
si = SubIndex(n("vc", vc), -1, vec(uw(8), 10))
assert not check(si)
def test_type_eq():
assert equal(UnknownType(), UnknownType())
assert equal(ClockType(), ClockType())
assert equal(uw(10), uw(10))
assert equal(sw(10), sw(10))
assert equal(vec(uw(10), 8), vec(uw(10), 8))
assert equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), True)),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), True)))
def test_write_port_index_wrong():
mem_ref = n("m", vec(uw(8), 10))
mw = DefMemWritePort("mw", mem_ref, s(2, w(8)), n("clock", ClockType()))
assert not check(mw)
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mw = DefMemWritePort("mw", mem_ref, n("a", vec(uw(1), 10)),
n("clock", ClockType()))
assert not check(mw)
def test_mux_basis():
mux = Mux(n("c", uw(1)), n("a", uw(8)), n("b", uw(8)), uw(8))
assert check(mux)
serialize_equal(mux, "mux(c, a, b)")
mux = Mux(u(1, w(1)), n("b", vec(sw(8), 10)), n("c", vec(sw(8), 10)),
vec(sw(8), 10))
assert check(mux)
serialize_equal(mux, 'mux(UInt<1>("h1"), b, c)')
def test_read_port_index_wrong():
mem_ref = n("m", vec(uw(8), 10))
mr = DefMemReadPort("mr", mem_ref, s(2, w(8)), n("clock", ClockType()))
assert not check(mr)
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mr = DefMemReadPort("mr", mem_ref, n("a", vec(uw(1), 10)),
n("clock", ClockType()))
assert not check(mr)
def test_write_port_basis():
mem_ref = n("m", vec(uw(8), 10))
mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", ClockType()))
assert check(mw)
serialize_stmt_equal(mw, 'write mport mw = m[UInt<8>("h2")], clock')
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), n("clock", ClockType()))
assert check(mw)
serialize_stmt_equal(mw, 'write mport mw = m[a], clock')
def test_read_port_basis():
mem_ref = n("m", vec(uw(8), 10))
mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", ClockType()))
assert check(mr)
serialize_stmt_equal(mr, 'read mport mr = m[UInt<8>("h2")], clock')
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), n("clock", ClockType()))
assert check(mr)
serialize_stmt_equal(mr, 'read mport mr = m[a], clock')
def test_sub_index_basis():
vc = vec(uw(8), 10)
si = SubIndex(n("vc", vc), 5, uw(8))
assert check(si)
serialize_equal(si, "vc[5]")
vc = vec(vec(uw(8), 10), 20)
si = SubIndex(n("vc", vc), 19, vec(uw(8), 10))
assert check(si)
serialize_equal(si, "vc[19]")
def test_sub_access_basis():
vc = vec(uw(8), 10)
sa = SubAccess(n("vc", vc), u(2, w(3)), uw(8))
assert check(sa)
serialize_equal(sa, 'vc[UInt<3>("h2")]')
vc = vec(uw(8), 10)
sa = SubAccess(n("vc", vc), n("a", uw(8)), uw(8))
assert check(sa)
serialize_equal(sa, 'vc[a]')
def vec_gen():
rand_num = random.randint(1, 100)
seed = random.choices(population=[1, 2, 3, 4],
weights=[0.4, 0.4, 0.1, 0.1],
k=1)[0]
if seed == 1:
return vec(uw_gen(), rand_num)
elif seed == 2:
return vec(sw_gen(), rand_num)
elif seed == 3:
return vec(vec_gen(), rand_num)
elif seed == 4:
return vec(bdl_gen(), rand_num)
def test_write_port_mem_wrong():
mem_ref = n("m", bdl(a=(vec(uw(8), 10), False)))
mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", ClockType()))
assert not check(mw)
mem_ref = n("m", uw(9))
mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), n("clock", ClockType()))
assert not check(mw)
def test_read_port_mem_wrong():
mem_ref = n("m", bdl(a=(vec(uw(8), 10), False)))
mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", ClockType()))
assert not check(mr)
mem_ref = n("m", uw(9))
mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), n("clock", ClockType()))
assert not check(mr)
def test_register_basis():
r1 = DefRegister("r1", uw(8), n("clock", ClockType()))
assert check(r1)
serialize_stmt_equal(r1, 'reg r1 : UInt<8>, clock')
r2 = DefRegister("r2", vec(uw(8), 10), n("clock", ClockType()))
assert check(r2)
serialize_stmt_equal(r2, 'reg r2 : UInt<8>[10], clock')
def test_mux_cond_type_wrong():
mux = Mux(n("c", uw(2)), n("a", uw(8)), n("b", uw(8)), uw(8))
assert not check(mux)
mux = Mux(n("c", sw(1)), n("a", uw(8)), n("b", uw(8)), uw(8))
assert not check(mux)
mux = Mux(n("c", vec(uw(1), 1)), n("a", uw(8)), n("b", uw(8)), uw(8))
assert not check(mux)
def test_type_neq():
assert not equal(UnknownType(), ClockType())
assert not equal(UnknownType(), uw(10))
assert not equal(UnknownType(), sw(10))
assert not equal(UnknownType(), vec(uw(10), 8))
assert not equal(UnknownType(), vec(sw(10), 8))
assert not equal(UnknownType(),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(ClockType(), UnknownType())
assert not equal(ClockType(), uw(10))
assert not equal(ClockType(), sw(10))
assert not equal(ClockType(), vec(uw(10), 8))
assert not equal(ClockType(), vec(sw(10), 8))
assert not equal(ClockType(),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(uw(10), UnknownType())
assert not equal(uw(10), ClockType())
assert not equal(uw(10), uw(8))
assert not equal(uw(10), sw(10))
assert not equal(uw(10), sw(10))
assert not equal(uw(10), vec(uw(10), 8))
assert not equal(uw(10), vec(sw(10), 8))
assert not equal(uw(10),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(sw(10), UnknownType())
assert not equal(sw(10), ClockType())
assert not equal(sw(10), sw(8))
assert not equal(sw(10), uw(10))
assert not equal(sw(10), uw(10))
assert not equal(sw(10), vec(uw(10), 8))
assert not equal(sw(10), vec(sw(10), 8))
assert not equal(sw(10),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(vec(uw(10), 8), UnknownType())
assert not equal(vec(uw(10), 8), ClockType())
assert not equal(vec(uw(10), 8), sw(8))
assert not equal(vec(uw(10), 8), uw(10))
assert not equal(vec(uw(10), 8), uw(10))
assert not equal(vec(uw(10), 8), vec(uw(8), 8))
assert not equal(vec(uw(10), 8), vec(uw(10), 9))
assert not equal(vec(uw(10), 8), vec(sw(10), 8))
assert not equal(vec(uw(10), 8),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
UnknownType())
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
ClockType())
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
sw(8))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
uw(10))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
uw(10))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
vec(sw(10), 8))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
bdl(a=(vec(uw(10), 8), True), b=(uw(10), False)))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
bdl(a=(vec(uw(10), 2), False), b=(uw(10), False)))
assert not equal(bdl(a=(uw(3), False), b=(uw(10), False)),
bdl(a=(uw(3), False), b=(uw(10), False), c=(sw(2), True)))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
bdl(b=(uw(10), False), a=(vec(uw(10), 8), False)))
def test_register_clock_wrong():
r1 = DefRegister("r1", uw(8), n("clock", uw(1)))
assert not check(r1)
r2 = DefRegister("r2", vec(uw(8), 10), n("clock", sw(1)))
assert not check(r2)
def test_sub_field_not_bundle():
sf = SubField(n("bd", uw(8)), "c", uw(8))
assert not check(sf)
sf = SubField(n("bd", vec(uw(8), 32)), "c", bdl(c=(uw(8), True)))
assert not check(sf)
def test_memory_type_wrong():
mem = DefMemory("m", bdl(a=(vec(uw(8), 10), False)))
assert not check(mem)
mem = DefMemory("m", uw(9))
assert not check(mem)
def test_sub_index_non_vector():
si = SubIndex(n("vc", uw(8)), 5, uw(1))
assert not check(si)
si = SubIndex(n("vc", bdl(a=(vec(uw(8), 10), True))), 19, vec(uw(8), 10))
assert not check(si)
