def test_per_route_exclusiveness(self):
alone = pyalone.Alone()
hicann = HICANNOnWafer(X(5), Y(5))
alone.add(hicann)
source = pyalone.L1BusOnWafer(hicann, HLineOnHICANN(5))
target = pyalone.Target(hicann, vertical)
routes = alone.find_routes(source, target)
self.assertEqual(1, len(routes))
routes = alone.find_routes(
source, target, pyalone.Alone.SWITCH_EXCLUSIVENESS_PER_ROUTE)
self.assertEqual(8, len(routes))
source = pyalone.L1BusOnWafer(hicann, VLineOnHICANN(5))
target = pyalone.Target(hicann, horizontal)
routes = alone.find_routes(source, target)
self.assertEqual(1, len(routes))
routes = alone.find_routes(
source, target, pyalone.Alone.SWITCH_EXCLUSIVENESS_PER_ROUTE)
self.assertEqual(2, len(routes))
source = pyalone.L1BusOnWafer(hicann, VLineOnHICANN(5))
target = pyalone.Target(hicann, vertical)
routes = alone.find_routes(source, target)
self.assertEqual(1, len(routes))
routes = alone.find_routes(
source, target, pyalone.Alone.SWITCH_EXCLUSIVENESS_PER_ROUTE)
self.assertEqual(1, len(routes))
def main():
parser = argparse.ArgumentParser()
parser.add_argument('--source-hicann',
required=True,
type=parse_hicann,
metavar='<enum>|<x>,<y>',
help='source HICANNOnWafer')
parser.add_argument('--source-hline',
required=False,
type=int,
help='source HLineOnHICANN')
parser.add_argument('--source-vline',
required=False,
type=int,
help='source VLineOnHICANN')
parser.add_argument('--target-hicann',
required=True,
type=parse_hicann,
metavar='<enum>|<x>,<y>',
help='target HICANNOnWafer')
parser.add_argument('--target-vertical',
action='store_true',
help='target should be VLineOnHICANN')
parser.add_argument('--without-hicann',
default=[],
type=parse_hicann,
nargs="+",
metavar='<enum>|<x>,<y>',
help='unavailable HICANNOnWafer')
args = parser.parse_args()
pylogging.reset()
pylogging.default_config(date_format='absolute')
alone = pyalone.Alone()
for hicann in iter_all(HICANNOnWafer):
if hicann in args.without_hicann:
continue
alone.add(hicann)
if args.source_hline is not None:
line = HLineOnHICANN(args.source_hline)
elif args.source_vline is not None:
line = VLineOnHICANN(args.source_vline)
else:
parser.error('Please specify one of --source-hline / --source-vline')
source = pyalone.L1BusOnWafer(args.source_hicann, line)
target = pyalone.Target(args.target_hicann,
vertical if args.target_vertical else horizontal)
routes = alone.find_routes(source, target)
for route in routes:
print(route)
def test_basic_route(self):
alone = pyalone.Alone()
hicann1 = HICANNOnWafer(X(5), Y(5))
hicann2 = HICANNOnWafer(X(6), Y(5))
alone.add(hicann1)
alone.add(hicann2)
source = pyalone.L1BusOnWafer(
hicann1,
SendingRepeaterOnHICANN(3).toHLineOnHICANN())
target = pyalone.Target(hicann2, horizontal)
routes = alone.find_routes(source, target)
self.assertEqual(1, len(routes))
for route in routes:
self.assertFalse(route.empty())
self.assertEqual(hicann1, route.source_hicann())
self.assertEqual(hicann2, route.target_hicann())
return routes
def test_dnc_merger_to_left(self):
alone = pyalone.Alone()
hicann_left = HICANNOnWafer(X(20), Y(14))
hicann_right = HICANNOnWafer(X(21), Y(14))
alone.add(hicann_left)
alone.add(hicann_right)
merger = DNCMergerOnHICANN(2)
target = pyalone.Target(hicann_left, vertical)
routes = alone.find_routes(hicann_right, merger, target)
self.assertEqual(len(routes), 1)
for route in routes:
self.assertFalse(route.empty())
self.assertEqual(hicann_right, route.source_hicann())
self.assertEqual(hicann_left, route.target_hicann())
segments = list(route)
self.assertEqual(hicann_right, segments[0])
self.assertEqual(merger, segments[1])
self.assertEqual(hicann_left, segments[2])