def build_handshaked_fifo(self, build_dir):
DATA_WIDTH = 8
accessible_signals = [
# (signal_name, read_only, is_signed, type_width)
("clk", 0, 0, 1),
("dataIn_data", 0, 0, DATA_WIDTH),
("dataIn_rd", 1, 0, 1),
("dataIn_vld", 0, 0, 1),
("dataOut_data", 1, 0, DATA_WIDTH),
("dataOut_rd", 0, 0, 1),
("dataOut_vld", 1, 0, 1),
("rst_n", 0, 0, 1),
("size", 1, 0, 3),
# (("fifo_inst", "clk"), 1, 0, 1),
# (("fifo_inst", "dataIn_data"), 1, 0, DATA_WIDTH),
# (("fifo_inst", "dataIn_wait"), 1, 0, 1),
# (("fifo_inst", "dataIn_en"), 1, 0, 1),
# (("fifo_inst", "dataOut_data"), 1, 0, DATA_WIDTH),
# (("fifo_inst", "dataOut_wait"), 1, 0, 1),
# (("fifo_inst", "dataOut_en"), 1, 0, 1),
# (("fifo_inst", "rst_n"), 0, 1, 1),
# (("fifo_inst", "size"), 1, 1, 3),
(("fifo_inst", "memory"), 1, 0, [3, DATA_WIDTH]),
(("fifo_inst", "fifo_read"), 1, 0, 1),
(("fifo_inst", "fifo_write"), 1, 0, 1),
]
files = ["fifo.v", "HandshakedFifo.v"]
return build_sim(files, accessible_signals, self, build_dir,
"HandshakedFifo")
def build_sim(self, build_dir, DW, top_name):
accessible_signals = [
# (signal_name, read_only, is_signed, type_width)
("inp", 0, 0, DW),
("outp", 1, 0, DW),
]
files = [
top_name + ".v",
]
return build_sim(files, accessible_signals, self, build_dir, top_name)
def cntr_build(self, build_dir):
"""
Build simulator for Cntr.v in specified dir
"""
accessible_signals = [
# (signal_name, read_only, is_signed, type_width)
("clk", 0, 0, 1),
("en", 0, 0, 1),
("rst", 0, 0, 1),
("val", 1, 0, 2),
]
verilog_files = ["Cntr.v"]
return build_sim(verilog_files, accessible_signals, self, build_dir, "Cntr")
def hw_build(self, build_dir):
"""
Build simulator for HandshakedWire.v in specified dir
"""
accessible_signals = [
# (signal_name, read_only, is_signed, type_width)
("clk", 0, 0, 1),
("rst_n", 0, 0, 1),
("dataIn_data", 0, 0, 8),
("dataIn_rd", 0, 0, 1),
("dataIn_vld", 1, 0, 1),
("dataOut_data", 1, 0, 8),
("dataOut_rd", 0, 0, 1),
("dataOut_vld", 1, 0, 1),
]
verilog_files = ["HandshakedWire.v"]
return build_sim(verilog_files, accessible_signals, self,
build_dir, "HandshakedWire")
def build_I2c_wire(self, build_dir):
accessible_signals = [
# (signal_name, read_only, is_signed, type_width)
("i_scl_i", 1, 0, 1),
("i_scl_o", 0, 0, 1),
("i_scl_t", 0, 0, 1),
("i_sda_i", 1, 0, 1),
("i_sda_o", 0, 0, 1),
("i_sda_t", 0, 0, 1),
("o_scl_i", 0, 0, 1),
("o_scl_o", 1, 0, 1),
("o_scl_t", 1, 0, 1),
("o_sda_i", 0, 0, 1),
("o_sda_o", 1, 0, 1),
("o_sda_t", 1, 0, 1),
]
verilog_files = ["I2c_wire.v"]
sim = build_sim(verilog_files, accessible_signals, self, build_dir,
"I2c_wire")
i, o = I2C(sim.io, "i"), I2C(sim.io, "o")
return sim, i, o
