def after_run(self, sim):
for sim_gear in sim.sim_gears:
module = sim_gear.gear
if module.definition == decouple_din:
if not module.queue.empty():
if 'data_in_decouple' in self.hooks:
self.hooks['data_in_decouple'](module)
log.error(f'Data left in decouple: {module.name}')
for p in module.in_ports:
status = self.get_port_status(p)
if status == "active":
src_port = get_source_producer(p, sim=True).consumers[0]
if src_port.gear.definition == const:
# Skip constants since they are never done
continue
if 'not_ack' in self.hooks:
self.hooks['not_ack'](module, p)
log.error(
f'{src_port.gear.name}.{src_port.basename} -> {module.name}.{p.basename} was not acknowledged'
)
if status == "waited":
src_port = self.blockers[p]
if 'waiting' in self.hooks:
self.hooks['waiting'](module, p)
log.debug(
f'{p.gear.name}.{p.basename} waiting on {src_port.gear.name}.{src_port.basename}'
)
def test_fir_random_type(impl, seed, do_cosim):
# Set random seed
set_seed(seed)
log.info(f'{__name__} impl: {impl}, seed: {seed}')
fixp_w = random.randint(16, 32)
int_w = random.randint(1, 3)
t_b = Fixp[int_w, fixp_w]
log.info(
f'{__name__} FIR input type t_b: {t_b} min: {t_b.fmin}, max: {t_b.fmax}'
)
seq = []
# generate multiple constant sequences of certain size
for i in range(10):
num = np.random.uniform(t_b.fmin, t_b.fmax)
for i in range(50):
seq.append(num)
# add a random sequence of certain size
seq.extend(random_seq(t_b, 100))
# genrate random numbers in [-1,1)
# seq = np.random.random(size=(100, )) * 2 - 1
log.debug(f'Generated sequence: {seq}')
res = fir_sim(impl, t_b, seq, do_cosim=do_cosim)
def iir_compare(x, y):
diff = abs(x - y)
dev = 1e-3
log.debug(f'{__name__}, exp:{y}, got:{x}')
log.debug(f'{__name__} deviation:{diff}')
if (diff > dev):
log.warning(f'{__name__} deviation error {diff}')
return diff < dev
def fir_compare(x, y):
diff = abs(x - y)
dev = 1e-3
log.debug(f'fir_compare Result exp: {y}, got: {x}')
log.debug(f'fir_compare Result deviation {diff}')
if (diff > dev):
log.warning(f'fir_compare Result deviation error {diff}')
return diff < dev
def test_fir_random(impl, seed, do_cosim):
# Set random seed
set_seed(seed)
log.info(f'Running {__name__} impl: {impl}, seed: {seed}')
t_b = Fixp[1, 15]
# genrate random numbers in [-1,1)
seq = np.random.random(size=(100, )) * 2 - 1
log.debug(f'Generated sequence: {seq}')
res = fir_sim(impl, t_b, seq, do_cosim=do_cosim)
def before_run(self, sim):
self.sock = socket.socket(socket.AF_UNIX, socket.SOCK_STREAM)
if self.run_cosim:
import uuid
filename = str(uuid.uuid4())
else:
filename = "svsock.s"
self.port = os.path.join(tempfile.gettempdir(), filename)
if os.path.exists(self.port):
os.remove(self.port)
self.sock.bind(self.port)
# Listen for incoming connections
# self.sock.listen(len(self.gear.in_ports) + len(self.gear.out_ports))
self.sock.listen(1)
self.build()
# if self.rebuild:
# self.build()
# else:
# self.kwds['nobuild'] = True
if not self.run_cosim:
self.invoke_cosim()
self.conn, addr = self.sock.accept()
else:
self.sock.settimeout(5)
self.cosim_pid = self.invoke_cosim()
ret = None
while ret is None:
try:
self.conn, addr = self.sock.accept()
break
except socket.timeout:
ret = self.cosim_pid.poll()
if ret is not None:
log.error(
f'Cosimulator error: {ret}. Check log File "{self.outdir}/log.log"'
)
raise CosimulatorStartError
msg = self.conn.recv(1024)
port_name = msg.decode()
log.debug(f"Connection received for {port_name}")
def find_target_cons(intf):
# Who is consumer port? Case when not broadcast!
# cons_rtl_port = intf.consumers[0]
end_c = get_end_consumer(intf)
if len(end_c) != 1:
if len(end_c) > 1:
log.debug(f'Find target cons: found broadcast')
return None
cons_rtl_port = end_c[0]
cons_rtl_node, port_id = cons_rtl_port.node, cons_rtl_port.index
cons_gear = cons_rtl_node.gear
cons_port = cons_gear.in_ports[port_id]
return cons_port
def test_iir_direct(tmpdir, impl, seed, do_cosim):
reg['sim/rand_seed'] = seed
random.seed(reg['sim/rand_seed'])
log.info(
f'Running test_fir_direct tmpdir: {tmpdir}, impl: {impl}, seed: {seed}'
)
reg['sim/clk_freq'] = 100000
t = list(range(reg['sim/clk_freq']))[0:100]
fs = reg['sim/clk_freq']
f1 = 1000
f2 = 70000
seq = []
for n in t:
seq.append(1 * sin(2 * pi * f1 / fs * n) +
0.1 * sin(2 * pi * f2 / fs * n))
sos = signal.butter(N=5,
Wn=30000 / 100000,
btype='lowpass',
analog=False,
output='sos')
a, b = [], []
for s in sos:
b.append(list(s[0:3]))
a.append(list(s[3:]))
t_coef = Fixp[5, 32]
b = [[t_coef(coef) for coef in section] for section in b]
a = [[t_coef(coef) for coef in section] for section in a]
gain = [Fixp[2, 23](1)] * len(b)
ref = signal.sosfilt(sos, seq)
fp_ref = [float(r) for r in ref]
log.debug(f'Generated sequence: {seq}')
drv(t=Fixp[5, 24], seq=seq) \
| impl(a=a, b=b, gain=gain, ogain=Fixp[5, 24](1)) \
| Float \
| check(ref=fp_ref[:len(seq)], cmp=lambda x, y: abs(x - y) < 1e-3)
if do_cosim:
cosim(f'{impl}', 'verilator', outdir=tmpdir, timeout=1000)
sim(tmpdir, check_activity=False)
def cosim_activity(self, g, top_name):
outdir = reg['results-dir']
activity_path = os.path.join(outdir, 'activity.log')
if not os.path.isfile(activity_path):
return
with open(activity_path, 'r') as log:
for line in log:
activity_name = line.rpartition(': ')[0]
activity_name = activity_name.replace('top.dut.',
f'{top_name}/')
activity_name = activity_name.rpartition('.')[0]
activity_name = activity_name.replace('_i.', '/')
gear_name, _, intf_name = activity_name.rpartition('/')
# Const always has valid high
const_regex = r'.*_const(?P<num>\d+)_s'
const_regex_one = r'.*_const_s'
if not (re.match(const_regex, intf_name)
or re.match(const_regex_one, intf_name)):
log.error(f'Cosim spy not acknowledged: {activity_name}')
if self.draw_graph:
bc_regex = r'.*_bc_(?P<num>\d+).*'
if re.match(bc_regex, intf_name):
log.debug(
f'Activity monitor cosim: bc not supported {activity_name}'
)
continue
intf = find_target_intf(gear_name, intf_name)
if intf is None:
log.error(
f'Cannot find matching interface for {activity_name}'
)
continue
if intf.is_broadcast:
log.debug(f'Intf bc not supported {activity_name}')
continue
try:
prod_gear = find_target_prod(intf)
set_blocking_node(g, prod_gear)
except (KeyError, AttributeError):
log.debug(f'Cannot find node for {activity_name}')
try:
cons_port = find_target_cons(intf)
set_blocking_edge(g, cons_port)
except (KeyError, AttributeError):
log.debug(f'Cannot find edge for {activity_name}')
def test_fir_limits(fixp_w, int_w, impl, seed, do_cosim):
"""[Drive filter with extreme values [min, 0 , max]
"""
# Set random seed
set_seed(seed)
log.info(f'Running {__name__} impl: {impl}, seed: {seed}')
t_b = Fixp[int_w, fixp_w]
log.info(
f'{__name__} FIR input type t_b: {t_b} min: {t_b.fmin}, max: {t_b.fmax}'
)
extremes = [[0 for i in range(50)]]
extremes.append([t_b.fmin for i in range(50)])
extremes.append([t_b.fmax for i in range(50)])
seq = random_choice_seq(extremes, 10)
log.debug(f'Generated sequence: {seq}')
res = fir_sim(impl, t_b, seq, do_cosim=do_cosim)
def iir_sim(impl,
t_coef,
t_in,
t_out,
seq,
target='build/iir',
do_cosim=False):
# create SOS referent filter and factors
sos = signal.butter(N=5,
Wn=30000 / 100000,
btype='lowpass',
analog=False,
output='sos')
# get a,b coefficient from the created filter
a, b = [], []
for s in sos:
b.append(list(s[0:3]))
a.append(list(s[3:]))
# convert coefficient to wanted Fixp type
b = [[t_coef(coef) for coef in section] for section in b]
a = [[t_coef(coef) for coef in section] for section in a]
log.debug(f'Generated B coeff: {b}')
log.debug(f'Generated A coeff: {a}')
gain = [t_in(1)] * len(b)
ref = signal.sosfilt(sos, seq)
# fp_ref = [float(r) for r in ref]
# saturate the results value to filter output type if needed
for i, r in enumerate(ref):
ref[i] = fixp_sat(t_out, float(r))
log.debug(f'Generated sequence: {seq}')
log.debug(f'Refferenc result: {ref}')
drv(t=t_in, seq=seq) \
| impl(a=a, b=b, gain=gain, ogain=t_in(1)) \
| Float \
| check(ref=ref[:len(seq)], cmp=iir_compare)
# optionally generate HDL code do co-simulation in verilator
if do_cosim:
cosim(f'{impl}', 'verilator', outdir=target, timeout=1000)
sim(target, check_activity=False)
return ref
def test_fir_sine(freq, impl, seed, do_cosim):
"""[Drive filter with sine signal at fs fs/2 and fs*2
"""
# Set random seed
set_seed(seed)
# set clock freq
reg['sim/clk_freq'] = freq
t = list(range(reg['sim/clk_freq']))[0:100]
fs = reg['sim/clk_freq']
f1 = freq / 100
log.info(f'Running {__name__} impl: {impl}, seed: {seed}')
t_b = Fixp[1, 15]
seq = [0 for i in range(10)]
seq.extend(sine_seq(f1, fs, 200, t_b))
seq.extend(sine_seq(f1, fs / 2, 100, t_b))
seq.extend(sine_seq(f1, fs * 2, 400, t_b))
seq.extend([0 for i in range(10)])
log.debug(f'Generated sequence: {seq}')
res = fir_sim(impl, t_b, seq, do_cosim=do_cosim)