def call_isinstance(arg, dtype):
if isinstance(dtype, ir.ResExpr):
dtype = dtype.val
if isinstance(arg, ir.ResExpr):
return Bool(isinstance(arg.val, dtype))
return ir.ResExpr(Bool(typeof(arg.dtype, dtype)))
async def clip(din: Queue[Tuple[{
'data': 't_data',
'size': Uint
}]],
*,
init=1) -> Queue['t_data']:
"""Clips the input transaction into two separate transactions by
sending the ``eot`` after a given number of data has passed (specified by
the ``size`` field of the :class:`Tuple`)
Args:
init: Initialization value for the counter
Returns:
A :class:`Queue` type whose data consists of the ``data`` field of
the :class:`Tuple` input
"""
cnt = din.dtype.data['size'](init)
pass_eot = Bool(True)
async for ((data, size), eot) in din:
yield (data, eot or ((cnt == size) and pass_eot))
if ((cnt == size) and pass_eot):
# to prevent wraparound if counter overflows
pass_eot = 0
cnt += 1
async def qfilt_union(din: Queue[Union, 'lvl'],
*,
fixsel=0,
filt_lvl=1) -> b'filt_type(din, lvl, fixsel)':
data_reg: din.dtype.data.data = din.dtype.data.data(0)
eot_reg: Uint[din.dtype.lvl] = Uint[din.dtype.lvl](0)
empty_reg: Bool = Bool(True)
curr_data: din.dtype.data.data
field_sel: Bool
while True:
async with din as d:
curr_data = d.data.data
field_sel = (d.data.ctrl == fixsel)
if all(d.eot[:filt_lvl]):
if field_sel:
if not empty_reg:
yield (data_reg, eot_reg)
yield (curr_data, d.eot)
elif not empty_reg:
yield (data_reg, d.eot)
empty_reg = True
elif field_sel:
if not empty_reg:
yield (data_reg, eot_reg)
# register
data_reg = curr_data
eot_reg = d.eot
empty_reg = False
def call_typeof(arg, dtype):
if isinstance(dtype, ir.ResExpr):
dtype = dtype.val
if not isinstance(arg, ir.ResExpr):
return ir.res_false
return ir.ResExpr(Bool(typeof(arg.val, dtype)))
async def test(din: Bool) -> Bool:
c = Bool(True)
while c:
async with din as c:
if c:
yield 0
else:
yield 1
def qround(din,
*,
fract=0,
cut_bits=b'get_cut_bits(din, fract)',
signed=b'din.signed') -> b'get_out_type(din, fract)':
res = code(din, Int if signed else Uint) + (Bool(1) << (cut_bits - 1))
return code(res >> cut_bits, module().tout)
def flatten_func(d, lvl):
dout_lvl = d.lvl - lvl
if dout_lvl == 0:
return d.data
else:
eot = d.eot[lvl + 1:] @ Bool(reduce(and_, d.eot[:lvl + 1]))
return Queue[type(d.data), dout_lvl](d.data, eot)
async def dreg(din, *, init=None) -> b'din':
data = din.dtype() if init is None else din.dtype(init)
valid = Bool(False) if init is None else Bool(True)
while True:
if valid:
yield data
try:
data = din.get_nb()
valid = True
except IntfEmpty:
valid = False
else:
data = await din.get()
valid = True
await clk()
async def test(din: Bool) -> Uint[4]:
c = Bool(True)
a = Uint[4](0)
while c:
async with din as c:
yield a
a += 1
yield 4
async def test(din: Bool) -> Bool:
c = Bool(True)
d = True
while c:
async with din as c:
if c:
d = 0
else:
d = 1
yield d
def test_directed(
cosim_cls,
wr0_delay,
rd0_delay,
wr1_delay,
rd1_delay,
dout_delay,
depth,
):
def wr0_delay_gen():
for _ in range(depth):
yield 0
while True:
yield wr0_delay
w_addr = 3
w_data = 8
wr_req_t = TWrReq[w_addr, Uint[w_data]]
rd_req_t = Uint[w_addr]
req_t = Union[rd_req_t, wr_req_t]
wr0_req_seq = [(i, i * 2) for i in range(depth)]
wr0_init_seq = [(i, 0) for i in range(depth)]
rd0_req_seq = list(range(depth))
rd1_req_seq = list(range(depth))
wr0_req = drv(t=wr_req_t, seq=wr0_init_seq + wr0_req_seq) \
| delay_gen(f=wr0_delay_gen())
rd0_req = drv(t=Uint[w_addr], seq=rd0_req_seq) \
| delay_gen(f=iter([depth])) \
| delay_rng(0, rd0_delay)
req0 = priority_mux(rd0_req, wr0_req)
req1 = ccat(drv(t=Uint[w_addr], seq=rd1_req_seq) \
| req_t.data \
| delay_gen(f=iter([depth])) \
| delay_rng(0, rd1_delay)
, Bool(False)) | req_t
verif(req0,
req1,
f=tdp(name='dut', sim_cls=cosim_cls, depth=depth),
ref=tdp(depth=depth),
delays=[delay_rng(0, dout_delay),
delay_rng(0, 0)])
sim()
async def test() -> Queue[Unit]:
yield Unit(), Bool(False)
yield Unit(), Bool(True)
def test_ResExpr():
e1 = ir.ResExpr(Bool(True))
e2 = ir.ResExpr(e1)
assert e2 is e1
def line(self, line=''):
if not line:
self.lines.append('')
else:
self.lines.append(f'{" "*self.indent}{line}')
def block(self, block):
for line in block.split('\n'):
self.line(line)
def __str__(self):
return '\n'.join(self.lines)
res_true = ir.ResExpr(Bool(True))
@dataclass
class BlockLines:
header: List = field(default_factory=list)
content: List = field(default_factory=list)
footer: List = field(default_factory=list)
def is_reg_id(expr):
return (isinstance(expr, ir.Name) and isinstance(expr.obj, ir.Variable) and expr.obj.reg)
class SVCompiler(HDLVisitor):
def __init__(self, ctx, var, writer, selected, lang, aux_funcs=None):
def some(din) -> Maybe['din']:
return ccat(din, Bool(True)) >> Maybe[din.dtype]
from pygears import Intf
def is_intf_id(expr):
return isinstance(expr, ir.Name) and typeof(expr.dtype, ir.IntfType)
# return (isinstance(expr, ir.Name) and isinstance(expr.obj, ir.Variable)
# and isinstance(expr.obj.val, Intf))
def add_to_list(orig_list, extension):
if extension:
orig_list.extend(
extension if isinstance(extension, list) else [extension])
res_true = ir.ResExpr(Bool(True))
res_false = ir.ResExpr(Bool(False))
class Scope:
def __init__(self, parent=None):
self.parent = None
self.child = None
self.items = {}
def subscope(self):
if self.child is None:
self.child = Scope(parent=self)
self.child.parent = self
return self.child
def call_is_type(arg):
if not isinstance(arg, ir.ResExpr):
return ir.res_false
return ir.ResExpr(Bool(is_type(arg.val)))
def test_bool():
assert Bool(2) == Uint[1](1)
assert Bool(0) == Uint[1](0)
assert type(Bool(0)) == Uint[1]