def test_numpy_policies(self):
import numpy
import pysthal
import pyhalco_hicann_v2
from pyhalbe import HICANN
w = pysthal.Wafer(pyhalco_hicann_v2.Wafer())
h = w[pyhalco_hicann_v2.HICANNOnWafer()]
addrs = numpy.array(numpy.random.randint(64, size=100),
dtype=numpy.ushort)
times = numpy.cumsum(numpy.random.poisson(10.0, size=100)) * 1.e-6
in_spikes = pysthal.Vector_Spike()
for addr, t in zip(addrs, times):
in_spikes.append(pysthal.Spike(HICANN.L1Address(addr), t))
link = pyhalco_hicann_v2.GbitLinkOnHICANN(3)
h.sendSpikes(link, in_spikes)
h.sortSpikes()
x = h.sentSpikes(link)
times_t, addrs_t = x.T
numpy.testing.assert_allclose(times,
times_t,
rtol=0.0,
atol=1.0 / 250e6)
numpy.testing.assert_array_equal(
addrs, numpy.array(addrs_t, dtype=numpy.ushort))
def test_MultiplePlaybackTraceHICANNLoopbackTest(self):
"""
tests whether playback can run multiple times.
using hicann loopback.
"""
self.hicann_loopback()
hicann_on_dnc = self.h.to_HICANNOnDNC()
for i in range(3):
pulse_events = []
pulse_address = FPGA.PulseAddress(self.dnc, hicann_on_dnc,
Coordinate.GbitLinkOnHICANN(0),
HICANN.Neuron.address_t(i))
# 5000 Pulses with ISI = 500 clks (2000 ns)
isi = 50 # every 500 cycles
start_offset = 500
num_pulses = 5000
for np in range(num_pulses):
pulse_events.append(
FPGA.PulseEvent(pulse_address,
isi * (np) + start_offset))
run_time_in_us = pulse_events[len(pulse_events) - 1].getTime(
) / FPGA.DNC_frequency_in_MHz + 1.e4
received_data = self.run_playback_and_trace_experiment(
FPGA.PulseEventContainer(pulse_events), run_time_in_us)
self.assertEqual(len(pulse_events), received_data.size(),
"run %s fails" % i)
# addresses sent and received pulses should be identical, only the channel flips
self.comparePulseListsAddress(
FPGA.PulseEventContainer(pulse_events),
received_data,
flip_channel=True)
def flip_GbitLink(channel):
"""
flips GbitLinkOnHICANN as it is expectd after loopback
"""
assert isinstance(channel, Coordinate.GbitLinkOnHICANN)
nn = int(channel)
return Coordinate.GbitLinkOnHICANN(int(nn / 2) * 2 + (not (nn % 2)))
def test_PulseFifoHICANNLoopbackTest(self):
self.hicann_loopback()
hicann_on_dnc = self.h.to_HICANNOnDNC()
pulse_events = []
pulse_address = FPGA.PulseAddress(self.dnc, hicann_on_dnc,
Coordinate.GbitLinkOnHICANN(2),
HICANN.Neuron.address_t(63))
# 5000 Pulses with ISI = 500 clks (2000 ns)
isi = 50 # every 500 cycles
start_offset = 500
num_pulses = 500
for np in range(num_pulses):
pulse_events.append(
FPGA.PulseEvent(pulse_address,
isi * (np) + start_offset))
run_time_in_us = pulse_events[len(pulse_events) -
1].getTime() / FPGA.DNC_frequency_in_MHz
received_data = FPGA.send_and_receive(
self.fpga, self.dnc, FPGA.PulseEventContainer(pulse_events), False,
int(run_time_in_us))
# sent and received pulses should be exactly equal - including timestamps!
self.comparePulseListsAddress(FPGA.PulseEventContainer(pulse_events),
received_data,
flip_channel=True)
def test_has_outbound_mergers(self):
import pyhalbe
import pysthal
from pyhalco_common import Enum
import pyhalco_hicann_v2 as C
wafer_c = C.Wafer(33)
gbitlink_c = C.GbitLinkOnHICANN(Enum(0))
fpga_on_wafer_c = C.FPGAOnWafer(Enum(0))
fpga_c = C.FPGAGlobal(fpga_on_wafer_c, wafer_c)
hicann_cs = [
C.HICANNGlobal(h, wafer_c) for h in fpga_c.toHICANNOnWafer()
]
hicann_c = hicann_cs[0]
hicann_on_dnc_c = hicann_c.toHICANNOnWafer().toHICANNOnDNC()
dnc_on_fpga_c = hicann_c.toDNCOnFPGA()
w = pysthal.Wafer()
h = w[hicann_c.toHICANNOnWafer()]
f = w[fpga_on_wafer_c]
self.assertFalse(f.hasOutboundMergers())
f[dnc_on_fpga_c][hicann_on_dnc_c].layer1[
gbitlink_c] = pyhalbe.HICANN.GbitLink.Direction.TO_DNC
self.assertTrue(f.hasOutboundMergers())
def test_SimpleSpinnakerIFHWTest(self):
"""
Test description:
Layer 2 is in HICANN loopback mode
We then configure the Spinnaker IF,
send pulses via the spinnaker pulse IF
and finally try to receive spikes on the other side.
"""
self.hicann_loopback()
hicann_on_dnc = self.h.to_HICANNOnDNC()
# we need to prepend one empty experiment
self.run_playback_and_trace_experiment(FPGA.PulseEventContainer(),
run_time_in_us=100)
pulse_address = FPGA.PulseAddress(self.dnc, hicann_on_dnc,
Coordinate.GbitLinkOnHICANN(0),
HICANN.Neuron.address_t(25))
up_sample_count = 100
down_sample_count = 10
# set up spinnaker stuff:
FPGA.set_spinnaker_pulse_upsampler(self.fpga, up_sample_count)
FPGA.set_spinnaker_pulse_downsampler(self.fpga, down_sample_count)
# routing table
spinn_pa = FPGA.SpinnInputAddress_t(0)
routing_table = FPGA.SpinnRoutingTable()
routing_table.set(spinn_pa, pulse_address)
FPGA.set_spinnaker_routing_table(self.fpga, routing_table)
# sender foncif
"""
ssc = FPGA.SpinnSenderConfig()
ssc.setActive(True)
ssc.setTargetIP(Coordinate.IPv4.from_string("192.168.1.127"))
ssc.setTargetPort(1851)
FPGA.set_spinnaker_sender_config(self.fpga, ssc)
"""
# WE SEND ONLY 1 PULSE
FPGA.add_spinnaker_pulse(self.fpga, spinn_pa)
FPGA.send_spinnaker_pulses(self.fpga)
time.sleep(0.0002)
# expecte pulse address is configured pulse address with dnc if channel flipped
exp_pa = FPGA.PulseAddress(pulse_address)
exp_pa.setChannel(flip_GbitLink(exp_pa.getChannel()))
# There should be exactly up_sample_count/down_sample_count pulses
num_expected_rec_pulses = int(up_sample_count / down_sample_count)
for i in range(num_expected_rec_pulses):
received_address = FPGA.get_received_spinnaker_pulse(self.fpga)
rpa = FPGA.PulseAddress(int(received_address))
self.assertEqual(
rpa, exp_pa, "Expected {exp}, actual {act}".format(exp=exp_pa,
act=rpa))
self.assertRaises(RuntimeError, FPGA.get_received_spinnaker_pulse,
self.fpga)
def test_SimpleRealtimeSpinnakerIFHWTest(self):
"""
Test description:
Layer 2 is in HICANN loopback mode
We then configure the Spinnaker IF,
send pulses via the realtime spinnaker pulse IF
and finally try to receive spikes on the other side.
"""
self.hicann_loopback()
hicann_on_dnc = self.h.to_HICANNOnDNC()
# we need to prepend one empty experiment
self.run_playback_and_trace_experiment(FPGA.PulseEventContainer(),
run_time_in_us=100)
pulse_address = FPGA.PulseAddress(self.dnc, hicann_on_dnc,
Coordinate.GbitLinkOnHICANN(0),
HICANN.Neuron.address_t(25))
up_sample_count = 100
down_sample_count = 10
# set up spinnaker stuff:
FPGA.set_spinnaker_pulse_upsampler(self.fpga, up_sample_count)
FPGA.set_spinnaker_pulse_downsampler(self.fpga, down_sample_count)
# routing table
spinn_pa = FPGA.SpinnInputAddress_t(0)
routing_table = FPGA.SpinnRoutingTable()
routing_table.set(spinn_pa, pulse_address)
FPGA.set_spinnaker_routing_table(self.fpga, routing_table)
# WE SEND ONLY 1 PULSE
spinn_pa = Realtime.spike_h()
spinn_pa.set_label(spinn_pa, 0) # uh, interface FIXME
FPGA.send_spinnaker_realtime_pulse(self.fpga, spinn_pa)
time.sleep(0.0002)
# expecte pulse address is configured pulse address with dnc if channel flipped
exp_pa = FPGA.PulseAddress(pulse_address)
exp_pa.setChannel(flip_GbitLink(exp_pa.getChannel()))
# There should be exactly up_sample_count/down_sample_count pulses
num_expected_rec_pulses = int(up_sample_count / down_sample_count)
sl = FPGA.get_received_realtime_pulses(self.fpga)
self.assertEqual(len(sl), num_expected_rec_pulses)
for sp in sl:
rpa = FPGA.PulseAddress(int(sp))
self.assertEqual(
rpa, exp_pa, "Expected {exp}, actual {act}".format(exp=exp_pa,
act=rpa))
def test_SpinnakerIF2TraceHWTest(self):
"""
Test description:
Layer 2 is in HICANN loopback mode
We then configure the Spinnaker IF,
send pulses via the spinnaker pulse IF
and finally try to receive spikes on the playback
"""
self.hicann_loopback()
hicann_on_dnc = self.h.to_HICANNOnDNC()
## we need to prepend one empty experiment
#self.run_playback_and_trace_experiment(FPGA.PulseEventContainer(), run_time_in_us=100)
pulse_address = FPGA.PulseAddress(self.dnc, hicann_on_dnc,
Coordinate.GbitLinkOnHICANN(0),
HICANN.Neuron.address_t(25))
up_sample_count = 100
down_sample_count = 10
# set up spinnaker stuff:
FPGA.set_spinnaker_pulse_upsampler(self.fpga, up_sample_count)
FPGA.set_spinnaker_pulse_downsampler(self.fpga, down_sample_count)
# routing table
spinn_pa = FPGA.SpinnInputAddress_t(42)
routing_table = FPGA.SpinnRoutingTable()
routing_table.set(spinn_pa, pulse_address)
FPGA.set_spinnaker_routing_table(self.fpga, routing_table)
runtime_in_us = 400
runtime_in_dnc_cycles = runtime_in_us * FPGA.DNC_frequency_in_MHz
FPGA.write_playback_pulses(self.fpga, FPGA.PulseEventContainer(),
runtime_in_dnc_cycles, 63)
FPGA.prime_experiment(self.fpga)
FPGA.start_experiment(self.fpga)
time.sleep(runtime_in_us / 2)
# WE SEND ONLY 1 PULSE
FPGA.add_spinnaker_pulse(self.fpga, spinn_pa)
FPGA.send_spinnaker_pulses(self.fpga)
time.sleep(runtime_in_us / 2)
received_data = FPGA.read_trace_pulses(self.fpga,
runtime_in_dnc_cycles).events
self.assertTrue(received_data.size() > 0)
def test_NeuronCurrentStimHWTest(self):
fgc = HICANN.FGControl()
fg_config = HICANN.FGConfig()
for block in [Enum(0), Enum(1)]:
block = Coordinate.FGBlockOnHICANN(block)
HICANN.set_fg_config(self.h, block, fg_config)
HICANN.set_fg_values(self.h, block, fgc.getBlock(block))
# 2nd: configure the neuron
nrn = HICANN.Neuron()
#HICANN.Neuron other_nrn = HICANN.Neuron()
nrn.address(HICANN.L1Address(42))
nrn.activate_firing(True)
nrn.enable_spl1_output(True)
nrn.enable_fire_input(False)
nrn.enable_aout(True)
nrn.enable_current_input(True)
nquad = HICANN.NeuronQuad()
nquad[Coordinate.NeuronOnQuad(X(0), Y(0))] = nrn
HICANN.set_denmem_quad(self.h, Coordinate.QuadOnHICANN(0), nquad)
# NEURON CONFIG
nrn_cfg = HICANN.NeuronConfig()
nrn_cfg.bigcap.set(Coordinate.top)
HICANN.set_neuron_config(self.h, nrn_cfg)
# set ANALOG
ac = HICANN.Analog()
ac.set_membrane_top_even(Coordinate.AnalogOnHICANN(0))
HICANN.set_analog(self.h, ac)
# CURRENT STIMULUS
fg_config = HICANN.FGConfig()
fg_config.pulselength = 15
for block in [Enum(0), Enum(1)]:
block = Coordinate.FGBlockOnHICANN(block)
HICANN.set_fg_config(self.h, block, fg_config)
stimulus = HICANN.FGStimulus()
stimulus.setContinuous(True)
stimulus[:40] = [800] * 40
stimulus[40:] = [0] * (len(stimulus) - 40)
HICANN.set_current_stimulus(self.h,
Coordinate.FGBlockOnHICANN(Enum(0)),
stimulus)
# READOUT PULSES!
#configure merger tree, phase
tree = HICANN.MergerTree()
#default settings are OK
HICANN.set_merger_tree(self.h, tree)
HICANN.set_phase(self.h)
dnc_mergers = HICANN.DNCMergerLine()
for i in range(8):
# rcv from HICANN
mer = Coordinate.DNCMergerOnHICANN(i)
dnc_mergers[mer].config = HICANN.Merger.RIGHT_ONLY
dnc_mergers[mer].slow = False
dnc_mergers[mer].loopback = False
HICANN.set_dnc_merger(self.h, dnc_mergers)
# DNC and dnc_if:
gbit = Coordinate.GbitLinkOnHICANN(0)
gl = HICANN.GbitLink()
gl.dirs[gbit.value()] = HICANN.GbitLink.Direction.TO_DNC
gr = DNC.GbitReticle()
gr[self.h.to_HICANNOnDNC()] = gl
HICANN.set_gbit_link(self.h, gl)
DNC.set_hicann_directions(self.fpga, self.dnc, gr)
HICANN.flush(self.h)
rec_pulses = FPGA.receive(self.fpga, self.dnc, 10000)
# 10 ms
print(str(rec_pulses.size()) + " packets received")
self.assertGreater(rec_pulses.size(), 0)
# Check for correct addrss of spikes
for np in range(rec_pulses.size()):
pulse = rec_pulses.get(np)
self.assertEqual(HICANN.L1Address(42), pulse.getNeuronAddress())
self.assertEqual(gbit, pulse.getChannel())
self.assertEqual(self.hicann, pulse.getChipAddress())
self.assertEqual(self.dnc, pulse.getDncAddress())
#turn off links
gl.dirs[0] = HICANN.GbitLink.Direction.OFF
gr[Coordinate.HICANNOnDNC(Enum(0))] = gl
HICANN.set_gbit_link(self.h, gl)
DNC.set_hicann_directions(self.fpga, self.dnc, gr)
HICANN.flush(self.h)
hicann.floating_gates.setNeuron(neuron_c, pyhalbe.HICANN.I_radapt, 1023 )
hicann.floating_gates.setNeuron(neuron_c, pyhalbe.HICANN.I_rexp ,0 )
hicann.floating_gates.setNeuron(neuron_c, pyhalbe.HICANN.I_spikeamp, 1023 )
hicann.floating_gates.setNeuron(neuron_c, pyhalbe.HICANN.V_exp ,0 )
hicann.floating_gates.setNeuron(neuron_c, pyhalbe.HICANN.V_syni ,511 )
hicann.floating_gates.setNeuron(neuron_c, pyhalbe.HICANN.V_syntci, 820 )
hicann.floating_gates.setNeuron(neuron_c, pyhalbe.HICANN.V_syntcx, 820 )
hicann.floating_gates.setNeuron(neuron_c, pyhalbe.HICANN.V_synx ,511 )
hicann.floating_gates.setNeuron(neuron_c, pyhalbe.HICANN.V_t ,819 )
# Configure two ADCs to read voltages of our neurons
hicann.enable_aout(neuron_c, Coordinate.AnalogOnHICANN(0))
# Setup Gbit Links and merger tree
sending_link = Coordinate.GbitLinkOnHICANN(0)
hicann.layer1[sending_link] = pyhalbe.HICANN.GbitLink.Direction.TO_HICANN
receiving_link = Coordinate.GbitLinkOnHICANN(1)
hicann.layer1[receiving_link] = pyhalbe.HICANN.GbitLink.Direction.TO_DNC
for m in iter_all(Coordinate.DNCMergerOnHICANN):
m = hicann.layer1[merger]
m.config = m.MERGE
m.slow = False
m.loopback = False
# sending link should loopback to receiving link
m = hicann.layer1[Coordinate.DNCMergerOnHICANN(sending_link.value())]
m.loopback = True
def test_spike_input(self):
self.marocco.wafer_cfg = os.path.join(self.temporary_directory,
"wafer_cfg.bin")
pynn.setup(marocco=self.marocco)
target = pynn.Population(1, pynn.IF_cond_exp, {})
params = [[1., 2., 3.], [4., 3., 2.]]
sources = [
pynn.Population(1, pynn.SpikeSourceArray, {'spike_times': times})
for times in params
]
for source in sources:
pynn.Projection(source, target,
pynn.AllToAllConnector(weights=0.004))
pynn.run(1000.)
results = self.load_results()
self.assertEqual(0, len(results.spike_times.get(target[0])))
for spike_times, pop in zip(params, sources):
self.assertSequenceEqual(spike_times,
results.spike_times.get(pop[0]))
spike_times.append(5.)
results.spike_times.add(pop[0], 5.)
self.assertSequenceEqual(spike_times, results.spike_times.get(pop[0]))
spike_times.extend([6., 7.])
results.spike_times.add(pop[0], [6., 7.])
self.assertSequenceEqual(spike_times, results.spike_times.get(pop[0]))
spike_times = [42., 123.]
results.spike_times.set(pop[0], spike_times)
self.assertSequenceEqual(spike_times, results.spike_times.get(pop[0]))
params[-1][:] = []
results.spike_times.clear(pop[0])
self.assertEqual(0, len(results.spike_times.get(pop[0])))
# Check that modifications are reflected in sthal config container
results.save(self.marocco.persist, overwrite=True)
self.marocco.skip_mapping = True
pynn.run(1000.)
import pysthal
wafer_cfg = pysthal.Wafer()
wafer_cfg.load(self.marocco.wafer_cfg)
for spike_times, pop in zip(params, sources):
item, = results.placement.find(pop[0])
address = item.address()
l1_address = address.toL1Address()
hicann_cfg = wafer_cfg[address.toHICANNOnWafer()]
hicann_cfg.sortSpikes()
raw_spikes = hicann_cfg.sentSpikes(
C.GbitLinkOnHICANN(address.toDNCMergerOnHICANN()))
raw_spikes = raw_spikes[raw_spikes[:, 1] == l1_address.value(), 0]
self.assertEqual(len(spike_times), len(raw_spikes))
pynn.end()
def test_IssueSpinnIFSendsOldPulsesHWTest(self):
"""
Test description:
Minimally adopted test from SimpleSpinnakerIFTest
Fails for the Issue, that if there are pulses available
in the FPGA upstream side, before the first UDP-Pulse arrived
in the FPGA: The prior pulses than fill the SpinnIF out fifo and
are then sent as soon as the SpinnIF gets activated.
we reproduce this by running a simple loopback experiment with 10
pulses, and then change the pulse address for teh normal spinn If
test.
"""
self.hicann_loopback()
hicann_on_dnc = self.h.to_HICANNOnDNC()
################################################
# we first test, whether the L2 connection works
################################################
pulse_events = []
pulse_address = FPGA.PulseAddress(self.dnc, hicann_on_dnc,
Coordinate.GbitLinkOnHICANN(0),
HICANN.Neuron.address_t(0))
# 5000 Pulses with ISI = 500 clks (2000 ns)
isi = 50 # every 500 cycles
start_offset = 500
num_pulses = 10
for np in range(num_pulses):
pulse_events.append(
FPGA.PulseEvent(pulse_address,
isi * (np) + start_offset))
run_time_in_us = pulse_events[len(pulse_events) -
1].getTime() / FPGA.DNC_frequency_in_MHz
received_data = self.run_playback_and_trace_experiment(
FPGA.PulseEventContainer(pulse_events), run_time_in_us)
# addresses sent and received pulses should be identical, only the channel flips
self.comparePulseListsAddress(FPGA.PulseEventContainer(pulse_events),
received_data,
flip_channel=True)
# L2 test done
################################################
# we now change the address
pulse_address = FPGA.PulseAddress(self.dnc, hicann_on_dnc,
Coordinate.GbitLinkOnHICANN(0),
HICANN.Neuron.address_t(1))
up_sample_count = 100
down_sample_count = 10
# set up spinnaker stuff:
FPGA.set_spinnaker_pulse_upsampler(self.fpga, up_sample_count)
FPGA.set_spinnaker_pulse_downsampler(self.fpga, down_sample_count)
# routing table
spinn_pa = FPGA.SpinnInputAddress_t(0)
routing_table = FPGA.SpinnRoutingTable()
routing_table.set(spinn_pa, pulse_address)
FPGA.set_spinnaker_routing_table(self.fpga, routing_table)
FPGA.add_spinnaker_pulse(self.fpga, spinn_pa)
FPGA.send_spinnaker_pulses(self.fpga)
time.sleep(0.0002)
# expecte pulse address is configured pulse address with dnc if channel flipped
exp_pa = FPGA.PulseAddress(pulse_address)
exp_pa.setChannel(flip_GbitLink(exp_pa.getChannel()))
num_expected_rec_pulses = int(up_sample_count / down_sample_count)
for i in range(num_expected_rec_pulses):
received_address = FPGA.get_received_spinnaker_pulse(self.fpga)
rpa = FPGA.PulseAddress(int(received_address))
self.assertEqual(
rpa, exp_pa, "Expected {exp}, actual {act}".format(exp=exp_pa,
act=rpa))
self.assertRaises(RuntimeError, FPGA.get_received_spinnaker_pulse,
self.fpga)