def add_upblk():
# This update block models the behavior of a 32-bit adder
s.out @= s.i + s.inlong
if s.out[3]:
s.state @= s.state + b1(1)
else:
s.state @= b1(0)
def add_upblk():
# This update block models the behavior of a 32-bit adder
s.out.x = s.i.x + s.inlong
s.out.y = s.i.y + s.inlong
if s.out.x[3] == "1":
s.state = s.state +b1(1)
else:
s.state = b1(0)
def reset( print_line_trace=False ):
if print_line_trace:
print()
top.reset = b1( active_high )
top.tick() # Tick twice to propagate the reset signal
if print_line_trace:
print( f"{top.simulated_cycles:3}r {top.line_trace()}" )
top.tick()
top.reset = b1( not active_high )
def sim_reset():
if print_line_trace:
print()
# cycle 0
top.reset @= b1( active_high )
up()
ff()
# cycle 1
up()
if print_line_trace:
print( f"{top._sim.simulated_cycles:3}r {top.line_trace()}" )
ff()
# cycle 2
up()
if print_line_trace:
print( f"{top._sim.simulated_cycles:3}r {top.line_trace()}" )
ff()
# cycle 3
top.reset @= b1( not active_high )
up()