def test_unpacked_signal_index(do_test):
    class A(Component):
        def construct(s):
            s.in_ = [InPort(Bits32) for _ in range(2)]
            s.out = OutPort(Bits64)

            @s.update
            def upblk():
                s.out = concat(s.in_[0], s.in_[1])

    a = A()
    a._ref_upblk_srcs = { 'upblk' : \
  """\
always_comb begin : upblk
  out = { in_[0], in_[1] };
end\
""" }

    # TestVectorSimulator properties
    def tv_in(m, tv):
        m.in_[0] = Bits32(tv[0])
        m.in_[1] = Bits32(tv[1])

    def tv_out(m, tv):
        assert m.out == Bits64(tv[2])

    a._test_vectors = [
        [42, 2, concat(Bits32(42), Bits32(2))],
        [-1, 42, concat(Bits32(-1), Bits32(42))],
        [-2, -1, concat(Bits32(-2), Bits32(-1))],
        [2, -2, concat(Bits32(2), Bits32(-2))],
    ]
    a._tv_in, a._tv_out = tv_in, tv_out
    a._ref_upblk_srcs_yosys = a._ref_upblk_srcs
    do_test(a)
def test_concat_mixed(do_test):
    class A(Component):
        def construct(s):
            s.in_ = InPort(Bits32)
            s.out = OutPort(Bits64)

            @s.update
            def upblk():
                s.out = concat(s.in_, Bits32(0))

    a = A()
    a._ref_upblk_srcs = { 'upblk' : \
  """\
always_comb begin : upblk
  out = { in_, 32'd0 };
end\
""" }

    # TestVectorSimulator properties
    def tv_in(m, tv):
        m.in_ = Bits32(tv[0])

    def tv_out(m, tv):
        assert m.out == Bits64(tv[1])

    a._test_vectors = [
        [42, concat(Bits32(42), Bits32(0))],
        [-1, concat(Bits32(-1), Bits32(0))],
        [-2, concat(Bits32(-2), Bits32(0))],
        [2, concat(Bits32(2), Bits32(0))],
    ]
    a._tv_in, a._tv_out = tv_in, tv_out
    a._ref_upblk_srcs_yosys = a._ref_upblk_srcs
    do_test(a)
def test_concat_constants(do_test):
    class A(Component):
        def construct(s):
            s.out = OutPort(Bits64)

            @s.update
            def upblk():
                s.out = concat(Bits32(42), Bits32(0))

    a = A()
    a._ref_upblk_srcs = { 'upblk' : \
  """\
always_comb begin : upblk
  out = { 32'd42, 32'd0 };
end\
""" }

    # TestVectorSimulator properties
    def tv_in(m, tv):
        pass

    def tv_out(m, tv):
        assert m.out == Bits64(tv[0])

    a._test_vectors = [
        [concat(Bits32(42), Bits32(0))],
    ]
    a._tv_in, a._tv_out = tv_in, tv_out
    a._ref_upblk_srcs_yosys = a._ref_upblk_srcs
    do_test(a)
Пример #4
0
def test_nested_struct(do_test):
    class C(BitStruct):
        def __init__(s, woof=2):
            s.woof = Bits32(woof)

    class B(BitStruct):
        def __init__(s, foo=42, bar=1):
            s.foo = Bits32(foo)
            s.bar = [Bits32(bar) for _ in range(2)]
            s.c = C()

    class A(Component):
        def construct(s):
            s.in_ = InPort(B)
            s.out = OutPort(Bits96)

            @s.update
            def upblk():
                s.out = concat(s.in_.bar[0], s.in_.c.woof, s.in_.foo)

    a = A()
    a._ref_upblk_srcs = { 'upblk' : \
  """\
always_comb begin : upblk
  out = { in_.bar[0], in_.c.woof, in_.foo };
end\
""" }

    # TestVectorSimulator properties
    def tv_in(m, tv):
        m.in_ = tv[0]

    def tv_out(m, tv):
        assert m.out == Bits96(tv[1])

    a._test_vectors = [
        [B(), concat(Bits32(1), Bits32(2), Bits32(42))],
        [B(0, 0), concat(Bits32(0), Bits32(2), Bits32(0))],
        [B(-1, -1), concat(Bits32(-1), Bits32(2), Bits32(-1))],
        [B(-1, 42), concat(Bits32(42), Bits32(2), Bits32(-1))],
        [B(42, 42), concat(Bits32(42), Bits32(2), Bits32(42))],
        [B(42, -1), concat(Bits32(-1), Bits32(2), Bits32(42))],
    ]
    a._tv_in, a._tv_out = tv_in, tv_out
    a._ref_upblk_srcs_yosys = { 'upblk' : \
  """\
always_comb begin : upblk
  out = { in___bar[0], in___c__woof, in___foo };
end\
""" }
    do_test(a)
Пример #5
0
 def upblk():
     s.out = concat(s, s.in_)
Пример #6
0
 def upblk():
     x = concat()
 def upblk():
     s.out = concat(s.in_[0], s.in_[1])
 def upblk():
     s.out = concat(s.in_, STATE_IDLE)
 def upblk():
     s.out = concat(s.in_, Bits32(0))
 def upblk():
     s.out = concat(Bits32(42), Bits32(0))
 def upblk():
     s.out = concat(s.in_1, s.in_2)
Пример #12
0
 def upblk():
     s.out = concat(s.in_.bar[0], s.in_.c.woof, s.in_.foo)
Пример #13
0
 def upblk():
     s.out = concat(s.in_.bar[0], s.in_.bar[1], s.in_.foo)
def test_nested_struct(do_test):
    @bitstruct
    class C:
        woof: Bits32

    @bitstruct
    class B:
        foo: Bits32
        bar: [Bits32] * 2
        c: C

    class A(Component):
        def construct(s):
            s.in_ = InPort(B)
            s.out = OutPort(Bits96)

            @s.update
            def upblk():
                s.out = concat(s.in_.bar[0], s.in_.c.woof, s.in_.foo)

    a = A()
    a._ref_upblk_srcs = { 'upblk' : \
  """\
always_comb begin : upblk
  out = { in_.bar[0], in_.c.woof, in_.foo };
end\
""" }

    # TestVectorSimulator properties
    def tv_in(m, tv):
        m.in_ = tv[0]

    def tv_out(m, tv):
        assert m.out == Bits96(tv[1])

    a._test_vectors = [
        [B(), concat(Bits32(0), Bits32(0), Bits32(0))],
        [
            B(0, [Bits32(0), Bits32(0)], C(5)),
            concat(Bits32(0), Bits32(5), Bits32(0))
        ],
        [
            B(-1, [Bits32(-1), Bits32(-2)], C(6)),
            concat(Bits32(-1), Bits32(6), Bits32(-1))
        ],
        [
            B(-1, [Bits32(42), Bits32(43)], C(7)),
            concat(Bits32(42), Bits32(7), Bits32(-1))
        ],
        [
            B(42, [Bits32(42), Bits32(43)], C(8)),
            concat(Bits32(42), Bits32(8), Bits32(42))
        ],
        [
            B(42, [Bits32(-1), Bits32(-2)], C(9)),
            concat(Bits32(-1), Bits32(9), Bits32(42))
        ],
    ]
    a._tv_in, a._tv_out = tv_in, tv_out
    a._ref_upblk_srcs_yosys = { 'upblk' : \
  """\
always_comb begin : upblk
  out = { in___bar[0], in___c__woof, in___foo };
end\
""" }
    do_test(a)
def test_packed_array_behavioral(do_test):
    @bitstruct
    class B:
        foo: Bits32
        bar: [Bits32] * 2

    class A(Component):
        def construct(s):
            s.in_ = InPort(B)
            s.out = OutPort(Bits96)

            @s.update
            def upblk():
                s.out = concat(s.in_.bar[0], s.in_.bar[1], s.in_.foo)

    a = A()
    a._ref_upblk_srcs = { 'upblk' : \
  """\
always_comb begin : upblk
  out = { in_.bar[0], in_.bar[1], in_.foo };
end\
""" }

    # TestVectorSimulator properties
    def tv_in(m, tv):
        m.in_ = tv[0]

    def tv_out(m, tv):
        assert m.out == Bits96(tv[1])

    a._test_vectors = [
        [B(), concat(Bits32(0), Bits32(0), Bits32(0))],
        [
            B(0, [Bits32(0), Bits32(0)]),
            concat(Bits32(0), Bits32(0), Bits32(0))
        ],
        [
            B(-1, [Bits32(-1), Bits32(-1)]),
            concat(Bits32(-1), Bits32(-1), Bits32(-1))
        ],
        [
            B(-1, [Bits32(42), Bits32(42)]),
            concat(Bits32(42), Bits32(42), Bits32(-1))
        ],
        [
            B(42, [Bits32(42), Bits32(42)]),
            concat(Bits32(42), Bits32(42), Bits32(42))
        ],
        [
            B(42, [Bits32(-1), Bits32(-1)]),
            concat(Bits32(-1), Bits32(-1), Bits32(42))
        ],
    ]
    a._tv_in, a._tv_out = tv_in, tv_out
    a._ref_upblk_srcs_yosys = { 'upblk' : \
  """\
always_comb begin : upblk
  out = { in___bar[0], in___bar[1], in___foo };
end\
""" }
    do_test(a)