def test_component_kw_args(do_test):
class A(Component):
def construct(s, foo, bar):
assert foo == Bits4(0)
assert bar == Bits16(42)
a = A(foo=Bits4(0), bar=Bits16(42))
a._ref_name = 'A__foo_0__bar_002a'
a._ref_src = \
"""\
component {}
(
port_decls:
interface_decls:
);
const_decls:
freevars:
wire_decls:
component_decls:
tmpvars:
upblk_srcs:
connections:
endcomponent
""".format( a._ref_name )
do_test(a)
def upblk():
if 1:
u = s.in_1 + Bits32(42)
s.out = u
else:
u = s.in_2 + Bits16(1)
s.out = u
def test_component_double_star_args_ungroup(do_test):
class A(Component):
def construct(s, foo, bar):
assert foo == Bits4(0)
assert bar == Bits16(42)
kwargs = {'foo': Bits4(0), 'bar': Bits16(42)}
a = A(**kwargs)
a._ref_name = 'A__foo_0__bar_002a'
a._ref_src = \
"""\
component {}
(
port_decls:
interface_decls:
);
const_decls:
freevars:
wire_decls:
component_decls:
tmpvars:
upblk_srcs:
connections:
endcomponent
""".format( a._ref_name )
do_test(a)
def test_component_mixed_kw_args(do_test):
class A(Component):
def construct(s, foo, bar, woo=Bits32(0)):
pass
a = A(Bits4(0), bar=Bits16(42))
a._ref_name = 'A__foo_0__bar_002a__woo_00000000'
a._ref_src = \
"""\
component {}
(
port_decls:
interface_decls:
);
const_decls:
freevars:
wire_decls:
component_decls:
tmpvars:
upblk_srcs:
connections:
endcomponent
""".format( a._ref_name )
do_test(a)
def test_queue_sw(): q = SimpleQueue() q.elaborate() assert q.enq.rdy() assert q.empty() assert not q.deq.rdy() q.enq( Bits16( 128 ) ) assert not q.enq.rdy() assert not q.empty() assert q.deq.rdy() assert q.deq() == Bits16( 128 ) assert q.enq.rdy() assert q.empty() assert not q.deq.rdy()
def test_component_star_args(do_test):
class A(Component):
def construct(s, *args):
assert args[0] == Bits4(0)
assert args[1] == Bits16(42)
args = [Bits4(0), Bits16(42)]
a = A(*args)
with expected_failure(RTLIRConversionError, "varargs are not allowed"):
do_test(a)
def test_component_double_star_args(do_test):
class A(Component):
def construct(s, **kwargs):
assert kwargs['foo'] == Bits4(0)
assert kwargs['bar'] == Bits16(42)
kwargs = {'foo': Bits4(0), 'bar': Bits16(42)}
a = A(**kwargs)
with expected_failure(RTLIRConversionError,
"keyword args are not allowed"):
do_test(a)
def up_wr_0_16():
s.A[0:16] @= Bits16(0xff)
def up_wr_As():
s.A[0:16] @= Bits16(0x1234)
def up_wr_At():
s.A[16:32] @= Bits16(0xff)
def up_wr_At():
s.A[8:24] @= Bits16(0xff)
def upblk():
u = Bits16(0)
s.out = u
def upblk():
if 1:
s.out = s.b.out
else:
s.out = Bits16(STATE_IDLE)
def upblk():
s.struct.foo = 0
s.struct.bar = Bits16(42)
def __init__(s, bar=42):
s.bar = Bits16(bar)
def up_wr_0_16(): s.x <<= 123 x.y = 123 s.A[0:16] @= Bits16( 0xff )
def construct(s, **kwargs):
assert kwargs['foo'] == Bits4(0)
assert kwargs['bar'] == Bits16(42)
def construct(s, *args):
assert args[0] == Bits4(0)
assert args[1] == Bits16(42)
def up_wr_y():
s.y @= Bits16(0x1234)
def upblk(): u = s.in_1 + Bits32(42) u = s.in_2 + Bits16(1) s.out = u
def up_wr_s_w():
s.x @= Bits16(0x1234)
def up_wr_16_30(): s.A[16:32] @= Bits16( 0xff ) s.B @= s.A[1:17]
def test_py_untyped_list():
with expected_failure(RTLIRConversionError, 'must have the same type'):
rt.get_rtlir([4, Bits16(42)])
def tv_in(m, tv):
m.in_ = Bits16(tv[0])
def construct(s, foo, bar):
assert foo == Bits4(0)
assert bar == Bits16(42)
def upblk():
if 1:
s.out = Bits16(STATE_IDLE)
else:
s.out = Bits16(STATE_WORK)
def test_chained_queue_incr_cl(): q = QueueIncrChained() src_msgs = [ Bits16( 0 ), Bits16( 1 ), Bits16( 2 ), Bits16( 3 ) ] sink_msgs = [ Bits16( 2 ), Bits16( 3 ), Bits16( 4 ), Bits16( 5 ) ] th = TestHarness( q, src_msgs, sink_msgs ) run_cl_sim( th )
def up_wr_8_24():
s.A[8:24] @= Bits16(0x1234)
def __init__( s, foo=42, bar=42, arr=1 ): s.foo = Bits32( foo ) s.inner = inner_struct(bar) s.packed_array = [[ Bits16(arr) for _ in range(2) ] for _ in range(3)]
def __init__(s, foo=0, bar=42):
s.foo = Bits32(foo)
s.bar = Bits16(bar)
