def test_1port(test_params, cmdline_opts):
msgs = test_params.msg_func(0x1000)
run_sim(
TestHarness(MagicMemoryCL, 1, [(req_cls, resp_cls)], [msgs[::2]],
[msgs[1::2]], test_params.stall, test_params.lat,
test_params.src_init, test_params.src_intv,
test_params.sink_init, test_params.sink_intv))
def test_xcel_rtl_fl():
th = TestHarness()
th.set_param( "top.construct",
MasterType = SomeMasterRTL,
MinionType = SomeMinionFL,
nregs = 8,
)
run_sim( th )
def test_20port(test_params, cmdline_opts):
msgs = [test_params.msg_func(0x1000 * i) for i in range(20)]
run_sim(
TestHarness(MagicMemoryCL, 20, [(req_cls, resp_cls)] * 20,
[x[::2] for x in msgs], [x[1::2] for x in msgs],
test_params.stall, test_params.lat, test_params.src_init,
test_params.src_intv, test_params.sink_init,
test_params.sink_intv))
def test_xcel_fl_rtl_nonblocking():
th = TestHarness()
th.set_param( "top.construct",
MasterType = SomeMasterNonBlockingFL,
MinionType = SomeMinionRTL,
nregs = 16,
)
run_sim( th )
def test_2port(test_params, cmdline_opts):
msgs0 = test_params.msg_func(0x1000)
msgs1 = test_params.msg_func(0x2000)
run_sim(
TestHarness(MagicMemoryCL, 2, [(req_cls, resp_cls)] * 2,
[msgs0[::2], msgs1[::2]], [msgs0[1::2], msgs1[1::2]],
test_params.stall, test_params.lat, test_params.src_init,
test_params.src_intv, test_params.sink_init,
test_params.sink_intv))
def test_xcel_rtl_cl():
th = TestHarness()
th.set_param(
"top.construct",
MasterType=SomeMasterRTL,
MinionType=SomeMinionCL,
nregs=8,
)
run_sim(th, max_cycles=1000)
def test_xcel_fl_cl_blocking():
th = TestHarness()
th.set_param(
"top.construct",
MasterType=SomeMasterBlockingFL,
MinionType=SomeMinionCL,
nregs=16,
)
run_sim(th, max_cycles=1000)
def run_sim(s, th, gen_test):
th.elaborate()
# Assemble the program
mem_image = assemble(gen_test())
# Load the program into memory
th.load(mem_image)
run_sim(th, s.__class__.cmdline_opts)
def test_gcd_rtl(test_params, cmdline_opts):
th = TestHarness(GcdUnitRTL())
th.set_param("top.src.construct",
msgs=test_params.msgs[::2],
initial_delay=test_params.src_delay,
interval_delay=test_params.src_delay)
th.set_param("top.sink.construct",
msgs=test_params.msgs[1::2],
initial_delay=test_params.sink_delay,
interval_delay=test_params.sink_delay)
run_sim(th, cmdline_opts, duts=['gcd'])
def test_stack_12bit(test_params, cmdline_opts):
th = TestHarness(12, 0, 0)
th.set_param("top.src.construct",
msgs=test_params.msgs[::2],
initial_delay=test_params.src_delay,
interval_delay=test_params.src_delay)
th.set_param("top.sink.construct",
msgs=test_params.msgs[1::2],
initial_delay=test_params.sink_delay,
interval_delay=test_params.sink_delay)
run_sim(th, cmdline_opts)
def test_gcd_fl(test_params):
th = TestHarness(GcdUnitFL())
th.set_param("top.src.construct",
msgs=test_params.msgs[::2],
initial_delay=test_params.src_delay,
interval_delay=test_params.src_delay)
th.set_param("top.sink.construct",
msgs=test_params.msgs[1::2],
initial_delay=test_params.sink_delay,
interval_delay=test_params.sink_delay)
run_sim(th)
def test_delay(QType, qsize, src_init, src_intv, sink_init, sink_intv,
arrival_time):
th = TestHarness(Bits16, QType, test_msgs, test_msgs)
th.set_param(
"top.src.construct",
initial_delay=src_init,
interval_delay=src_intv,
)
th.set_param("top.dut.construct", num_entries=qsize)
th.set_param(
"top.sink.construct",
initial_delay=sink_init,
interval_delay=sink_intv,
arrival_time=arrival_time,
)
run_sim(th)
def test_stack_8bit(test_params, cmdline_opts):
th = TestHarness(hard_bits=4, loopback=1,
queue_size=4) # all 0s = no additional modules
th.set_param("top.src.construct",
msgs=test_params.msgs[::2],
initial_delay=test_params.src_delay,
interval_delay=test_params.src_delay)
th.set_param("top.sink.construct",
msgs=test_params.msgs[1::2],
initial_delay=test_params.sink_delay,
interval_delay=test_params.sink_delay)
run_sim(th, cmdline_opts)
def test_read_write_mem(cmdline_opts):
rgen = random.Random()
rgen.seed(0x05a3e95b)
# Test data we want to write into memory
data = [rgen.randrange(-(2**31), 2**31) for _ in range(20)]
# Convert test data into byte array
data_bytes = struct.pack("<{}i".format(len(data)), *data)
# Create memory messages to read and verify memory contents
msgs = []
for i, item in enumerate(data):
msgs.extend([
req('rd', 0x1, 0x1000 + 4 * i, 0, 0),
resp('rd', 0x1, 0, item),
])
# Create test harness with above memory messages
th = TestHarness(MagicMemoryCL, 2, [(req_cls, resp_cls)] * 2,
[msgs[::2], []], [msgs[1::2], []], 0, 0, 0, 0, 0, 0)
th.elaborate()
# Write the data into the test memory
th.mem.write_mem(0x1000, data_bytes)
# Run the test
run_sim(th)
# Read the data back out of the test memory
result_bytes = th.mem.read_mem(0x1000, len(data_bytes))
# Convert result bytes into list of ints
result = list(struct.unpack("<{}i".format(len(data)), result_bytes))
# Compare result to original data
assert result == data
def test_reqresp_net(test_params):
ncaches = test_params.ncaches
max_in_flight = test_params.max_in_flight
init_delay = test_params.init
intv_delay = test_params.intv
src_msgs, sink_msgs = test_params.msg_func(test_params.ncaches)
th = TestHarness(ncaches, max_in_flight, src_msgs, sink_msgs)
th.set_param('top.mem.construct', latency=test_params.lat)
for i in range(ncaches):
th.set_param(
f'top.sink[{i}].construct',
initial_delay=init_delay[i],
interval_delay=intv_delay[i],
)
run_sim(th)
def test(test_params, cmdline_opts):
# instantiate test harness
top = TestHarness(SramMinionRTL())
# configure the src/sink messages
msgs = test_params.msg_func()
top.set_param("top.src.construct",
msgs=msgs[::2],
initial_delay=test_params.src,
interval_delay=test_params.src)
top.set_param("top.sink.construct",
msgs=msgs[1::2],
initial_delay=test_params.sink,
interval_delay=test_params.sink)
# run the simulation
run_sim(top, cmdline_opts, duts=['sram'])
def test_normal2_simple():
th = TestHarness(Bits16, NormalQueueRTL, test_msgs, test_msgs)
th.set_param("top.sink.construct", arrival_time=arrival_pipe)
th.set_param("top.dut.construct", num_entries=2)
run_sim(th, max_cycles=500)
def test_pipe1_simple(): th = TestHarness( Bits16, PipeQueueRTL, test_msgs, test_msgs ) th.set_param( "top.sink.construct", arrival_time = arrival_pipe ) th.set_param( "top.dut.construct", num_entries = 1 ) run_sim( th )
def test_pipe2_backpressure(): th = TestHarness( Bits16, PipeQueueRTL, test_msgs, test_msgs ) th.set_param( "top.sink.construct", initial_delay = 20 ) th.set_param( "top.dut.construct", num_entries = 2 ) run_sim( th )
def test_single_simple( QType ): th = TestHarness( Bits16, QType, test_msgs, test_msgs ) run_sim( th )
def test_mem_fl_cl_adapter():
class SomeMasterFL(Component):
def construct(s, base, has_loop=0):
s.mem = MemMasterIfcFL()
s.addr = 0x1000 + base
s.end = 0x1000 + base + 0x10
s.trace = " "
if has_loop == 1:
@update_once
def up_master_while():
s.trace = " "
while s.addr < s.end:
s.mem.write(s.addr, 4, 0xdead0000 | s.addr)
s.trace = "wr 0x{:x} ".format(s.addr)
x = s.mem.read(s.addr, 4)
s.trace = "rd 0x{:x} {}".format(s.addr, x)
s.addr += 4
else:
@update_once
def up_master_noloop():
s.trace = "# "
s.mem.write(s.addr, 4, 0xdead0000 | s.addr)
s.trace = "wr 0x{:x} ".format(s.addr)
x = s.mem.read(s.addr, 4)
s.trace = "rd 0x{:x} {}".format(s.addr, x)
s.addr += 4
def done(s):
return s.addr >= s.end
def line_trace(s):
return s.trace
class SomeMinionCL(Component):
def recv(s, msg):
assert s.entry is None
s.entry = msg
def recv_rdy(s):
return s.entry is None
def read(s, addr, nbytes):
nbytes = int(nbytes)
nbits = nbytes << 3
ret, shamt = Bits(nbits, 0), Bits(nbits, 0)
addr = int(addr)
end = addr + nbytes
for j in range(addr, end):
ret += Bits(nbits, s.memory[j]) << shamt
shamt += 8
return ret
def write(s, addr, nbytes, data):
tmp = int(data)
addr = int(addr)
end = addr + int(nbytes)
for j in range(addr, end):
s.memory[j] = tmp & 255
tmp >>= 8
def construct(s, req_class, resp_class):
s.mem = MemMinionIfcCL(req_class, resp_class, s.recv, s.recv_rdy)
s.entry = None
s.memory = bytearray(2**20)
@update_once
def up_process():
if s.entry is not None and s.mem.resp.rdy():
# Dequeue memory request message
req = s.entry
s.entry = None
len_ = int(req.len)
if not len_: len_ = req_class.data_nbits >> 3
if req.type_ == MemMsgType.READ:
resp = resp_class(req.type_, req.opaque, 0, req.len,
s.read(req.addr, len_))
elif req.type_ == MemMsgType.WRITE:
s.write(req.addr, len_, req.data)
resp = resp_class(req.type_, req.opaque, 0, 0, 0)
s.mem.resp(resp)
s.add_constraints(
U(up_process) < M(s.mem.req)) # definite pipe behavior
def line_trace(s):
return str(s.mem)
class TestHarness(Component):
def construct(s):
s.master = [SomeMasterFL(i * 0x222, i) for i in range(2)]
s.minion = [SomeMinionCL(*mk_mem_msg(8, 32, 32)) for _ in range(2)]
for i in range(2):
s.minion[i].mem //= s.master[i].mem
def line_trace(s):
return "|".join( [ x.line_trace() for x in s.master ] ) + " >>> " + \
"|".join( [ x.line_trace() for x in s.minion ] )
def done(s):
return all([x.done() for x in s.master])
# Run simulation
run_sim(TestHarness())
def test_single_simple(QType):
th = TestHarness(Bits16, QType, test_msgs, test_msgs)
run_sim(th, max_cycles=500)
def test_single_backpressure(QType):
th = TestHarness(Bits16, QType, test_msgs, test_msgs)
th.set_param("top.sink.construct", initial_delay=10, interval_delay=2)
run_sim(th, max_cycles=500)
def test_large_backpressure(QType, num_entries):
msgs = test_msgs * 8
th = TestHarness(Bits16, QType, msgs, msgs)
th.set_param("top.sink.construct", initial_delay=20)
th.set_param("top.dut.construct", num_entries=16)
run_sim(th, max_cycles=500)
def test_bypass2_sparse():
th = TestHarness(Bits16, BypassQueueRTL, test_msgs, test_msgs)
th.set_param("top.src.construct", interval_delay=3)
th.set_param("top.dut.construct", num_entries=2)
run_sim(th, max_cycles=500)
def test_bypass1_backpressure():
th = TestHarness(Bits16, BypassQueueRTL, test_msgs, test_msgs)
th.set_param("top.sink.construct", initial_delay=20)
th.set_param("top.dut.construct", num_entries=1)
run_sim(th, max_cycles=500)
def test_normal_simple():
th = TestHarness(Bits16, NormalQueueCL, test_msgs, test_msgs)
th.set_param("top.dut.construct", num_entries=1)
th.set_param("top.sink.construct", arrival_time=arrival_normal)
run_sim(th)
def test_delay_pipe_send(test_params, cmdline_opts):
msgs = test_params.msg_func()
run_sim(
TestHarness(DelayPipeSendCL, msgs[::2], msgs[1::2], test_params.lat,
test_params.src_lat, test_params.sink_lat))
def run_sim(s, th):
run_sim(th, s.__class__.cmdline_opts)
def test_bypass1_simple():
th = TestHarness(Bits16, BypassQueueRTL, test_msgs, test_msgs)
th.set_param("top.sink.construct", arrival_time=arrival_bypass)
th.set_param("top.dut.construct", num_entries=1)
run_sim(th, max_cycles=500)
