def test_direct_16x32(cmdline_opts): run_test_vector_sim( SramRTL(16, 32), [ header_str, # val type idx wdata rdata [1, 1, 0x0, 0x0000, '?'], # one at a time [1, 0, 0x0, 0x0000, '?'], [0, 0, 0x0, 0x0000, 0x0000], [1, 1, 0x0, 0xbeef, '?'], [1, 0, 0x0, 0x0000, '?'], [0, 0, 0x0, 0x0000, 0xbeef], [1, 1, 0x1, 0xcafe, '?'], [1, 0, 0x1, 0x0000, '?'], [0, 0, 0x0, 0x0000, 0xcafe], [1, 1, 0xf, 0x0a0a, '?'], [1, 0, 0xf, 0x0000, '?'], [0, 0, 0x0, 0x0000, 0x0a0a], [1, 1, 0xe, 0x0b0b, '?'], # streaming reads [1, 0, 0xe, 0x0000, '?'], [1, 0, 0xf, 0x0000, 0x0b0b], [1, 0, 0x1, 0x0000, 0x0a0a], [1, 0, 0x0, 0x0000, 0xcafe], [0, 0, 0x0, 0x0000, 0xbeef], [1, 1, 0xd, 0x0c0c, '?'], # streaming writes/reads [1, 0, 0xd, 0x0000, '?'], [1, 1, 0xc, 0x0d0d, 0x0c0c], [1, 0, 0xc, 0x0000, '?'], [1, 1, 0xb, 0x0e0e, 0x0d0d], [1, 0, 0xb, 0x0000, '?'], [0, 0, 0x0, 0x0000, 0x0e0e], ], cmdline_opts)
def test_direct_128x256(cmdline_opts): run_test_vector_sim( SramRTL(128, 256, mask_size=0), [ header_str, # val type idx wdata rdata [1, 1, 0x00, 0x00000000, '?'], # one at a time [1, 0, 0x00, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0x00000000], [1, 1, 0x00, 0xdeadbeef, '?'], [1, 0, 0x00, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0xdeadbeef], [1, 1, 0x01, 0xcafecafe, '?'], [1, 0, 0x01, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0xcafecafe], [1, 1, 0x2f, 0x0a0a0a0a, '?'], [1, 0, 0x2f, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0x0a0a0a0a], [1, 1, 0x2e, 0x0b0b0b0b, '?'], # streaming reads [1, 0, 0x2e, 0x00000000, '?'], [1, 0, 0x2f, 0x00000000, 0x0b0b0b0b], [1, 0, 0x01, 0x00000000, 0x0a0a0a0a], [1, 0, 0x00, 0x00000000, 0xcafecafe], [0, 0, 0x00, 0x00000000, 0xdeadbeef], [1, 1, 0x2d, 0x0c0c0c0c, '?'], # streaming writes/reads [1, 0, 0x2d, 0x00000000, '?'], [1, 1, 0x2c, 0x0d0d0d0d, 0x0c0c0c0c], [1, 0, 0x2c, 0x00000000, '?'], [1, 1, 0x2b, 0x0e0e0e0e, 0x0d0d0d0d], [1, 0, 0x2b, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0x0e0e0e0e], ], cmdline_opts)
def test_direct_32x256(cmdline_opts): run_test_vector_sim( SramRTL(32, 256), [ header_str, # val type idx wdata rdata [1, 1, 0x00, 0x00000000, '?'], # one at a time [1, 0, 0x00, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0x00000000], [1, 1, 0x00, 0xdeadbeef, '?'], [1, 0, 0x00, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0xdeadbeef], [1, 1, 0x01, 0xcafecafe, '?'], [1, 0, 0x01, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0xcafecafe], [1, 1, 0x1f, 0x0a0a0a0a, '?'], [1, 0, 0x1f, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0x0a0a0a0a], [1, 1, 0x1e, 0x0b0b0b0b, '?'], # streaming reads [1, 0, 0x1e, 0x00000000, '?'], [1, 0, 0x1f, 0x00000000, 0x0b0b0b0b], [1, 0, 0x01, 0x00000000, 0x0a0a0a0a], [1, 0, 0x00, 0x00000000, 0xcafecafe], [0, 0, 0x00, 0x00000000, 0xdeadbeef], [1, 1, 0x1d, 0x0c0c0c0c, '?'], # streaming writes/reads [1, 0, 0x1d, 0x00000000, '?'], [1, 1, 0x1c, 0x0d0d0d0d, 0x0c0c0c0c], [1, 0, 0x1c, 0x00000000, '?'], [1, 1, 0x1b, 0x0e0e0e0e, 0x0d0d0d0d], [1, 0, 0x1b, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0x0e0e0e0e], ], cmdline_opts)
def test_large(cmdline_opts): run_test_vector_sim(RegIncr(), [ ('in_ out*'), [0xa0, '?'], [0xb3, 0xa1], [0xc6, 0xb4], [0x00, 0xc7], ], cmdline_opts)
def test_overflow(cmdline_opts): run_test_vector_sim(RegIncr(), [ ('in_ out*'), [0x00, '?'], [0xfe, 0x01], [0xff, 0xff], [0x00, 0x00], ], cmdline_opts)
def test_small(cmdline_opts): run_test_vector_sim(RegIncr(), [ ('in_ out*'), [0x00, '?'], [0x03, 0x01], [0x06, 0x04], [0x00, 0x07], ], cmdline_opts)
def test_large(cmdline_opts): run_test_vector_sim(RegIncr2stage(), [ ('in_ out*'), [0xa0, '?'], [0xb3, '?'], [0xc6, 0xa2], [0x00, 0xb5], [0x00, 0xc8], ], cmdline_opts)
def test_small(cmdline_opts): run_test_vector_sim(RegIncr2stage(), [ ('in_ out*'), [0x00, '?'], [0x03, '?'], [0x06, 0x02], [0x00, 0x05], [0x00, 0x08], ], cmdline_opts)
def test_basic(): run_test_vector_sim( SortUnitFL(), [ header_str, # in in in in in out out out out out # val [0] [1] [2] [3] val [0] [1] [2] [3] [ 0, 0, 0, 0, 0, 0, x, x, x, x ], [ 1, 4, 2, 3, 1, 0, x, x, x, x ], [ 0, 0, 0, 0, 0, 1, 1, 2, 3, 4 ], [ 0, 0, 0, 0, 0, 0, x, x, x, x ], ] )
def test_random(nbits, cmdline_opts): test_vector_table = [('in0', 'in1', 'out_min*', 'out_max*')] for i in range(20): in0 = randint(0, 2**nbits - 1) in1 = randint(0, 2**nbits - 1) test_vector_table.append([in0, in1, min(in0, in1), max(in0, in1)]) run_test_vector_sim(MinMaxUnit(nbits), test_vector_table, cmdline_opts)
def test_basic(cmdline_opts): run_test_vector_sim(MinMaxUnit(8), [ ('in0 in1 out_min* out_max*'), [0x00, 0x00, 0x00, 0x00], [0x04, 0x03, 0x03, 0x04], [0x09, 0x06, 0x06, 0x09], [0x0a, 0x0f, 0x0a, 0x0f], [0xff, 0x10, 0x10, 0xff], ], cmdline_opts)
def test_random(cmdline_opts): test_vector_table = [('in_', 'out*')] last_result = '?' for i in range(20): rand_value = random.randint(0, 0xff) test_vector_table.append([rand_value, last_result]) last_result = rand_value + 1 run_test_vector_sim(RegIncr(), test_vector_table, cmdline_opts)
def test_random(cmdline_opts): test_vector_table = [('in_', 'out*')] last_result_0 = '?' last_result_1 = '?' for i in range(20): rand_value = b8(random.randint(0, 0xff)) test_vector_table.append([rand_value, last_result_1]) last_result_1 = last_result_0 last_result_0 = b8(rand_value + 2, trunc_int=True) run_test_vector_sim(RegIncr2stage(), test_vector_table, cmdline_opts)
def test_basic(cmdline_opts): run_test_vector_sim( SortUnitFlatRTL(), [ header_str, # in in in in in out out out out out # val [0] [1] [2] [3] val [0] [1] [2] [3] [0, 0, 0, 0, 0, 0, x, x, x, x], [1, 4, 2, 3, 1, 0, x, x, x, x], [0, 0, 0, 0, 0, 0, x, x, x, x], [0, 0, 0, 0, 0, 0, x, x, x, x], [0, 0, 0, 0, 0, 1, 1, 2, 3, 4], [0, 0, 0, 0, 0, 0, x, x, x, x], ], cmdline_opts)
def test_sequential_rom_rtl(): run_test_vector_sim( SequentialROMRTL(Bits32, 8, [8, 7, 6, 5, 4, 3, 2, 1], num_ports=2), [ ('raddr[0]', 'rdata[0]*', 'raddr[1]', 'rdata[1]*'), [1, '?', 5, '?'], [2, 7, 7, 3], [0, 6, 0, 1], ]) run_test_vector_sim( SequentialROMRTL(Bits32, 8, [8, 7, 6, 5, 4, 3, 2, 1], num_ports=2), [ ('raddr[0]', 'rdata[0]*', 'raddr[1]', 'rdata[1]*'), [1, '?', 5, '?'], [2, 7, 7, 3], [0, 6, 0, 1], ], { 'dump_vcd': 'test_rom', 'test_verilog': 'ones', 'dump_vtb': '' })
def test_combinational_rom_rtl(): run_test_vector_sim( CombinationalROMRTL(Bits32, 8, [8, 7, 6, 5, 4, 3, 2, 1], num_ports=2), [ ('raddr[0]', 'rdata[0]*', 'raddr[1]', 'rdata[1]*'), [1, 7, 5, 3], [2, 6, 7, 1], ]) run_test_vector_sim( CombinationalROMRTL(Bits32, 8, [8, 7, 6, 5, 4, 3, 2, 1], num_ports=2), [ ('raddr[0]', 'rdata[0]*', 'raddr[1]', 'rdata[1]*'), [1, 7, 5, 3], [2, 6, 7, 1], ], { 'dump_vcd': 'test_rom', 'test_verilog': 'ones', 'dump_vtb': '' })
def test_direct_128x256_mask4(cmdline_opts): header_str = \ ( "port0_val", "port0_type", "port0_wben", "port0_idx", "port0_wdata", "port0_rdata*" ) run_test_vector_sim( SramRTL(128, 256, mask_size=4), [ header_str, # val type wben idx wdata rdata [1, 1, 0b0001, 0x00, 0x00000000, '?'], # one at a time [1, 0, 0b0001, 0x00, 0x00000000, '?'], [0, 0, 0b0001, 0x00, 0x00000000, 0x00000000], [1, 1, 0b0001, 0x00, 0xdeadbeef, '?'], [1, 0, 0b0001, 0x00, 0x00000000, '?'], [0, 0, 0b0001, 0x00, 0x00000000, 0xdeadbeef], [1, 1, 0b0001, 0x01, 0xcafecafe, '?'], [1, 0, 0b0001, 0x01, 0x00000000, '?'], [0, 0, 0b0001, 0x00, 0x00000000, 0xcafecafe], [1, 1, 0b0001, 0x2f, 0x0a0a0a0a, '?'], [1, 0, 0b0001, 0x2f, 0x00000000, '?'], [0, 0, 0b0001, 0x00, 0x00000000, 0x0a0a0a0a], [1, 1, 0b0001, 0x2e, 0x0b0b0b0b, '?'], # streaming reads [1, 0, 0b0001, 0x2e, 0x00000000, '?'], [1, 0, 0b0001, 0x2f, 0x00000000, 0x0b0b0b0b], [1, 0, 0b0001, 0x01, 0x00000000, 0x0a0a0a0a], [1, 0, 0b0001, 0x00, 0x00000000, 0xcafecafe], [0, 0, 0b0001, 0x00, 0x00000000, 0xdeadbeef], [1, 1, 0b0001, 0x2d, 0x0c0c0c0c, '?'], # streaming writes/reads [1, 0, 0b0001, 0x2d, 0x00000000, '?'], [1, 1, 0b0001, 0x2c, 0x0d0d0d0d, 0x0c0c0c0c], [1, 0, 0b0001, 0x2c, 0x00000000, '?'], [1, 1, 0b0001, 0x2b, 0x0e0e0e0e, 0x0d0d0d0d], [1, 0, 0b0001, 0x2b, 0x00000000, '?'], [0, 0, 0b0001, 0x00, 0x00000000, 0x0e0e0e0e], ], cmdline_opts)
def test_random(cmdline_opts, data_nbits, num_entries): run_test_vector_sim(SramRTL(data_nbits, num_entries), gen_rand_tvec(data_nbits, num_entries), cmdline_opts)
def test_sort_fl( test_params ): nstages = test_params.nstages inputs = test_params.inputs run_test_vector_sim( SortUnitFL(), mk_test_vector_table( 1, inputs ) )
def test_sorted(cmdline_opts): run_test_vector_sim(SortUnitFlatRTL(), mk_test_vector_table(3, tvec_sorted), cmdline_opts)
def test_random(nbits, cmdline_opts): tvec_random = [[randint(0, 2**nbits - 1) for _ in range(4)] for _ in range(20)] run_test_vector_sim(SortUnitFlatRTL(nbits), mk_test_vector_table(3, tvec_random), cmdline_opts)
def test_sort_cl(test_params): nstages = test_params.nstages inputs = test_params.inputs run_test_vector_sim(SortUnitCL(nstages=nstages), mk_test_vector_table(nstages, inputs))
def test_random( n, cmdline_opts ): run_test_vector_sim( RegIncrNstage( nstages=n ), mk_test_vector_table( n, sample(range(0xff),20) ), cmdline_opts )
def test_sort_fl_random( n ): run_test_vector_sim( SortUnitFL(), mk_test_vector_table( 1, tvec_random ) )
def test_dups(cmdline_opts): run_test_vector_sim(SortUnitFlatRTL(), mk_test_vector_table(3, tvec_dups), cmdline_opts)
def test( test_params, cmdline_opts ): nstages = test_params.nstages inputs = test_params.inputs run_test_vector_sim( RegIncrNstage( nstages ), mk_test_vector_table( nstages, inputs ), cmdline_opts )
def test_sort_cl_random(n): run_test_vector_sim(SortUnitCL(nstages=n), mk_test_vector_table(n, tvec_random))