def test_select_with_5_wires(self):
val_width = 5
sels, sel_vals = utils.make_inputs_and_values(5, exact_bitwidth=1, test_vals=50)
mux_ins, vals = utils.make_inputs_and_values(5, exact_bitwidth=val_width, test_vals=50)
out = pyrtl.Output(val_width, "out")
out <<= muxes.prioritized_mux(sels, mux_ins)
actual = utils.sim_and_ret_out(out, sels + mux_ins, sel_vals + vals)
expected = [pri_mux_actual(sel, val) for sel, val in zip(zip(*sel_vals), zip(*vals))]
self.assertEqual(actual, expected)
def test_one_wire(self):
a = pyrtl.WireVector(1)
b = pyrtl.WireVector(10)
x = muxes.prioritized_mux([a], [b])
self.assertIs(b, x)
def test_different_sel_and_val_lengths(self):
a = pyrtl.WireVector(1)
with self.assertRaises(pyrtl.PyrtlError):
x = muxes.prioritized_mux([a], [a, a])
def test_invalid_select_width(self):
a = pyrtl.WireVector(2)
b = pyrtl.WireVector(2)
c = pyrtl.WireVector(10)
with self.assertRaises(pyrtl.PyrtlError):
x = muxes.prioritized_mux([a, b], [c, c])
def test_empty(self):
with self.assertRaises(pyrtl.PyrtlError):
x = muxes.prioritized_mux([], [])