def setUp(self):
"""
Set up the unit test:
A full reticle is allocated and complelty configured with zeroed
floating gates.
"""
if None in (self.WAFER, self.DNC):
raise unittest.SkipTest("No DNC selected, skipping hardware test")
return
self.data_adcs = {}
# Dump data in case of an error in setup
self.save_data()
self.wafer = pysthal.Wafer(self.WAFER)
self.reset_hicann_config()
db = pysthal.MagicHardwareDatabase()
self.wafer.connect(db)
for hicann_c in self.hicanns:
hicann = self.wafer[hicann_c]
for analog in Coordinate.iter_all(Coordinate.AnalogOnHICANN):
key = self.adc_key(hicann_c, analog)
try:
cfg = hicann.getADCConfig(analog)
self.data_adcs[key] = (cfg.coord.value(),
cfg.channel.value(), [])
except RuntimeError:
self.data_adcs[key] = (None, None, [])
self.wafer.configure(pysthal.ParallelHICANNv4Configurator())
def f_hicann(hicann):
"""prints Hicann related variables"""
ghicann = Coordinate.HICANNGlobal(hicann, WAFER)
out = print_hicann(ghicann)
fpga = ghicann.toFPGAOnWafer()
dnc = ghicann.toDNCGlobal()
for coordinate in [
fpga, dnc,
dnc.toDNCOnFPGA(),
dnc.toPowerCoordinate(),
hicann.toHICANNOnDNC()
]:
has_id = getattr(coordinate, "id", None)
if has_id:
out += "\t{} ({})\n".format(coordinate, coordinate.id())
else:
out += "\t{}\n".format(coordinate)
try:
import pysthal
db = pysthal.MagicHardwareDatabase()
ip = db.get_fpga_ip(Coordinate.HICANNGlobal(hicann, WAFER))
port = 1700 + dnc.toDNCOnFPGA().value()
out += "\t{} {}".format(ip.to_string(), port)
except Exception:
pass
return out
def record_membrane(output_dir, hicann, aout, placement_item, wafer_cfg,
params):
"""
:type hicann: HICANNOnWafer
:type aout: AnalogOnHICANN
"""
import pysthal
import Coordinate as C
logical_neuron = placement_item.logical_neuron()
hicann_cfg = wafer_cfg[hicann]
hicann_cfg.enable_aout(logical_neuron.front(), aout)
db = pysthal.MagicHardwareDatabase()
wafer_cfg.connect(db)
configurator = pysthal.HICANNv4Configurator()
wafer_cfg.configure(configurator)
adc = hicann_cfg.analogRecorder(aout)
recording_time = params["duration"] / 1e3 / 1e4
adc.setRecordingTime(recording_time)
adc.activateTrigger()
runner = pysthal.ExperimentRunner(recording_time)
wafer_cfg.start(runner)
if adc.hasTriggered():
v = adc.trace()
t = adc.getTimestamps()
membrane = np.vstack((t, v)).T
else:
membrane = np.empty(0)
address = placement_item.address()
link = C.GbitLinkOnHICANN(address.toDNCMergerOnHICANN())
spikes = hicann_cfg.receivedSpikes(link)
if len(spikes):
spikes = spikes[spikes[:, 1] == address.toL1Address()]
return (membrane, spikes)
def test_MagicHardwareDatabase(self):
"""
Test using the magic hardware database with custom backend file
"""
yaml = """
---
wafer: 0
setuptype: facetswafer
fpgas:
- fpga: 0
ip: 10.11.12.13
- fpga: 1
ip: "127.127.127.127" # BOGUS ips, otherwise the orignal database is loaded and we don't see it
"""
settings = pysthal.Settings.get()
original_yaml_path = settings.yaml_hardware_database_path
def cleanup(settings, path):
settings.yaml_hardware_database_path = path
self.addCleanup(cleanup, settings, original_yaml_path)
db = pysthal.YAMLHardwareDatabase()
with tempfile.NamedTemporaryFile(mode="w+") as f:
f.write(yaml)
f.flush()
settings.yaml_hardware_database_path = f.name
db = pysthal.MagicHardwareDatabase()
self.assertEqual(
db.get_fpga_ip(FPGAGlobal(FPGAOnWafer(0), Wafer(0))),
IPv4.from_string("10.11.12.13"))
self.assertEqual(
db.get_fpga_ip(FPGAGlobal(FPGAOnWafer(1), Wafer(0))),
IPv4.from_string("127.127.127.127"))
fpga_c = hicann_c.toFPGAOnWafer()
dnc_c = fpga_c.toDNCOnWafer()
wafer = pysthal.Wafer(wafer_c)
wafer.drop_defects()
fpga = wafer[fpga_c]
pll_frequency = args.pll * 1e6
fpga.commonFPGASettings().setPLL(pll_frequency)
fpga.commonFPGASettings().setSynapseArrayReset(args.zero_syn)
hicann = wafer[hicann_c]
if args.zero_fg:
set_floating_gate_to_zero(hicann)
# blacklist all but the HICANN under test
for h in C.iter_all(C.HICANNOnDNC):
if h.toHICANNOnWafer(fpga_c) != hicann_c:
fpga.setBlacklisted(h, True)
if args.jtag:
for h_hs in C.iter_all(C.HighspeedLinkOnDNC):
if h_hs.toHICANNOnDNC().toHICANNOnWafer(dnc_c) == hicann_c:
fpga.setHighspeed(h_hs.toHICANNOnDNC(), False)
wafer.connect(pysthal.MagicHardwareDatabase())
if not args.zero_fg:
wafer.configure(pysthal.JustResetHICANNConfigurator())
else:
wafer.configure()
print 'V_convoffx: ', h.floating_gates.getNeuron(
denmem, pyhalbe.HICANN.neuron_parameter.V_convoffx)
print 'V_threshold: ', h.floating_gates.getNeuron(
denmem, pyhalbe.HICANN.neuron_parameter.V_t)
print 'E_syni: ', h.floating_gates.getNeuron(
denmem, pyhalbe.HICANN.neuron_parameter.E_syni)
print 'E_synx: ', h.floating_gates.getNeuron(
denmem, pyhalbe.HICANN.neuron_parameter.E_synx)
print '#########################################################################'
h.use_big_capacitors(True)
h.set_speed_up_gl(pysthal.SpeedUp.NORMAL)
h.set_speed_up_gladapt(pysthal.SpeedUp.SLOW)
h.set_speed_up_radapt(pysthal.SpeedUp.SLOW)
db = pysthal.MagicHardwareDatabase()
import os
w.connect(db)
adc = h.analogRecorder(coord_analog)
recording_time = duration_ms / 1e3 / 1e4
adc.setRecordingTime(recording_time)
w.configure(pysthal.HICANNv4Configurator())
runner = pysthal.ExperimentRunner(recording_time)
adc.activateTrigger()
w.start(runner)
# Construct input spike train
spikes_raw = np.arange(20) * 1e-6 + 10e-6
more_spikes_raw = np.arange(20) * 1e-6 + spikes_raw[-1]*2
spikes_raw = np.concatenate([spikes_raw, more_spikes_raw])
duration = spikes_raw[-1] + 30e-6
spikes = pysthal.Vector_Spike()
for t in spikes_raw:
spikes.append(pysthal.Spike(in_addr, t))
hicann.sendSpikes(sending_link, spikes)
print(hicann)
# Connect to hardware
connection_db = pysthal.MagicHardwareDatabase()
wafer.connect(connection_db)
class NoneConfigurator(pysthal.HICANNConfigurator):
def config(self, fpga, h, hicann):
self.hicann_init(h)
self.config_synapse_array(h, hicann);
self.config_neuron_quads(h, hicann, True)
self.config_phase(h, hicann)
self.config_gbitlink(h, hicann)
self.config_synapse_drivers(h, hicann)
self.config_synapse_switch(h, hicann)
self.config_crossbar_switches(h, hicann)
def connect(self):
self.w.connect(pysthal.MagicHardwareDatabase())