Пример #1
0
def write_verilog(node, filename=None):
    visitor = VerilogModuleVisitor()
    modules = tuple(node.get_modules().values())

    module_ast_list = [
        visitor.visit(mod) for mod in modules
        if not isinstance(mod, module.StubModule)
    ]
    description = vast.Description(module_ast_list)
    source = vast.Source(filename, description)

    codegen = ASTCodeGenerator()
    main = codegen.visit(source)

    stub = [
        mod.get_code() for mod in modules
        if isinstance(mod, module.StubModule)
    ]

    code = ''.join([main] + stub)

    if filename:
        with open(filename, 'w') as f:
            f.write(code)
    return code
Пример #2
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 def get_combinational_equivalence_formal(self, module_name, state_count,
                                          dip_list):
     self.state_size_msb = state_count - 1
     self.dip_chk_module()
     self.ce_module(module_name, dip_list)
     self.ce_module_ext_formal()
     self.main = vast.Description([self.dip_chk, self.ce])
Пример #3
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 def get_dip_gen_formal(self, dip_list):
     self.uc_module(dip_list)
     self.uc_module_ext_formal()
     self.dip_gen_module()
     # self.dip_gen_module_uc()
     self.dip_chk_module()
     self.main = vast.Description([self.dip_gen, self.dip_chk, self.uc])
Пример #4
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 def get_combinational_equivalence(self, module_name, state_count,
                                   dip_list):
     # based on assumptions on next states and no assertions
     self.state_size_msb = state_count - 1
     self.dip_chk_module()
     self.ce_module(module_name, dip_list)
     self.ce_module_ext_sby()
     self.main = vast.Description([self.dip_chk, self.ce])
Пример #5
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def read_verilog_stubmodule(*filelist, **opt):
    module_dict = to_module_dict(*filelist, **opt)
    codegen = ASTCodeGenerator()
    stubs = collections.OrderedDict()
    for name, m in module_dict.items():
        description = vast.Description((m, ))
        source = vast.Source('', description)
        code = codegen.visit(source)
        stubs[name] = module.StubModule(name, code=code)
    return stubs
Пример #6
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def split_to_verilog(node, list_file_name=None):
    import veriloggen.verilog.to_verilog as to_verilog
    from veriloggen.core import module
    import pyverilog.vparser.ast as vast
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator

    obj = node.to_hook_resolved_obj()

    visitor = to_verilog.VerilogModuleVisitor()
    modules = tuple(obj.get_modules().values())

    run_files = []

    for mod in modules:
        if isinstance(mod, module.StubModule):
            code = mod.get_code()
            filename = mod.name + '.v'
            with open(filename, 'w') as f:
                print("Write file : ", filename)
                f.write("//File : " + filename)
                f.write("\n//This file is auto generated, do not edit!")
                f.write(code)
                run_files.append(filename)
        else:
            m = visitor.visit(mod)
            filename = m.name + '.v'
            description = vast.Description([m])
            source = vast.Source(filename, description)
            codegen = ASTCodeGenerator()
            main = codegen.visit(source)
            with open(filename, 'w') as f:
                print("Write file : ", filename)
                f.write("//File : " + filename)
                f.write("\n//This file is auto generated, do not edit!")
                f.write(main)
                run_files.append(filename)

    if list_file_name is not None:
        with open(list_file_name, 'w') as f:
            for name in run_files:
                f.write(name+"\n")
Пример #7
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 def get_keys_circuit_formal(self, dip_list, skip_cycles, equal_keys):
     # this module finds the agreeing keys
     self.dip_chk_module()
     self.fk_module(dip_list, skip_cycles, equal_keys)
     self.fk_module_ext_formal()
     self.main = vast.Description([self.dip_chk, self.ce])
Пример #8
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 def get_umc(self, dip_list):
     self.dip_chk_module()
     self.umc_module(dip_list)
     self.umc_module_ext_sby()
     self.dip_gen_module()
     self.main = vast.Description([self.dip_chk, self.dip_gen, self.umc])
Пример #9
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 def get_unique_completion(self, dip_list):
     self.uc_module(dip_list)
     self.uc_module_ext_sby()
     self.dip_gen_module_uc()
     self.dip_chk_module()
     self.main = vast.Description([self.dip_gen, self.dip_chk, self.uc])