import os import pyxir import logging from pyxir.graph.transformers import subgraph from ..target.components.DPUCZDX8G.som import xgraph_dpu_optimizer from ..target.components.DPUCZDX8G.som import xgraph_dpu_quantizer from ..target.components.DPUCZDX8G.som import xgraph_dpu_som_compiler logger = logging.getLogger('pyxir') def xgraph_dpuv2_som_build_func(xgraph, work_dir=os.getcwd(), **kwargs): # TODO here or in optimizer, both? # DPU layers are in NHWC format because of the tensorflow # intemediate structure we use to communicate with # DECENT/DNNC return subgraph.xgraph_build_func(xgraph=xgraph, target='dpuv2-som', xtype='DPU', layout='NHWC', work_dir=work_dir) pyxir.register_target('dpuv2-som', xgraph_dpu_optimizer, xgraph_dpu_quantizer, xgraph_dpu_som_compiler, xgraph_dpuv2_som_build_func)
# # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. import pyxir from pyxir.runtime import base from .components.DPUCADX8G.dpu_target import xgraph_dpu_build_func from .components.DPUCADX8G.dpu_target import xgraph_dpu_compiler from .components.DPUCADX8G.dpu_target import DPULayer from .components.DPUCADX8G.external_quantizer_tools import xgraph_dpu_external_quantizer from .components.DPUCADX8G.external_quantizer_tools import xgraph_dpu_external_quantizer_optimizer # Register target pyxir.register_target('DPUCADX8G', xgraph_dpu_external_quantizer_optimizer, xgraph_dpu_external_quantizer, xgraph_dpu_compiler, xgraph_dpu_build_func) # Register layer pyxir.register_op('cpu-np', 'DPU', base.get_layer(DPULayer)) # Register op support from .components.DPUCADX8G import dpu_op_support
from .components.DPUCZDX8G.common import xgraph_dpu_quantizer from .components.DPUCZDX8G.common import xgraph_dpu_optimizer from .components.DPUCZDX8G.common import xgraph_dpu_op_support_annotator from .components.DPUCZDX8G.ultra96 import xgraph_dpu_ultra96_build_func from .components.DPUCZDX8G.ultra96 import xgraph_dpu_ultra96_compiler from .components.DPUCZDX8G.zcu102 import xgraph_dpu_zcu102_build_func from .components.DPUCZDX8G.zcu102 import xgraph_dpu_zcu102_compiler from .components.DPUCZDX8G.zcu104 import xgraph_dpu_zcu104_build_func from .components.DPUCZDX8G.zcu104 import xgraph_dpu_zcu104_compiler # Register target pyxir.register_target('DPUCZDX8G-ultra96', xgraph_dpu_optimizer, xgraph_dpu_quantizer, xgraph_dpu_ultra96_compiler, xgraph_dpu_ultra96_build_func) # Register op support from .components.DPUCZDX8G import ultra96_op_support # Register target pyxir.register_target('DPUCZDX8G-zcu102', xgraph_dpu_optimizer, xgraph_dpu_quantizer, xgraph_dpu_zcu102_compiler, xgraph_dpu_zcu102_build_func) # Register op support from .components.DPUCZDX8G import zcu102_op_support
import os import pyxir import logging from pyxir.graph.transformers import subgraph from pyxir.contrib.target.DPUCZDX8G.ultra96 import xgraph_dpu_optimizer,\ xgraph_dpu_quantizer, xgraph_dpu_ultra96_compiler logger = logging.getLogger('pyxir') def xgraph_dpuv2_ultra96_build_func(xgraph, work_dir=os.getcwd(), **kwargs): # TODO here or in optimizer, both? # DPU layers are in NHWC format because of the tensorflow # intemediate structure we use to communicate with # DECENT/DNNC return subgraph.xgraph_build_func(xgraph=xgraph, target='dpuv2-ultra96', xtype='DPU', layout='NHWC', work_dir=work_dir) pyxir.register_target('dpuv2-ultra96', xgraph_dpu_optimizer, xgraph_dpu_quantizer, xgraph_dpu_ultra96_compiler, xgraph_dpuv2_ultra96_build_func)
def xgraph_dpu_zcu102_compiler(xgraph, **kwargs): meta = { "lib": "/usr/local/lib/libn2cube.so", # "vitis_dpu_kernel": "tf_resnet50_0", "pre_processing_pool": 4, "post_processing_pool": 4, "dpu_thread_pool": 3, "dpu_task_pool": 16 } # Vitis-AI 1.1 old_arch = "/opt/vitis_ai/compiler/arch/dpuv2/ZCU102/ZCU102.json" # Vitis-AI 1.2 - ... new_arch = "/opt/vitis_ai/compiler/arch/DPUCZDX8G/ZCU102/arch.json" if os.path.exists(new_arch): arch = new_arch else: arch = old_arch compiler = VAICompiler(xgraph, arch=arch, meta=meta, **kwargs) c_xgraph = compiler.compile() return c_xgraph pyxir.register_target('DPUCZDX8G-zcu102', xgraph_dpu_optimizer, xgraph_dpu_quantizer, xgraph_dpu_zcu102_compiler, xgraph_dpu_zcu102_build_func)
xtype='DPU', layout='NCHW', work_dir=work_dir) def xgraph_dpuv1_compiler(xgraph, **kwargs): # TODO: can we move to docker paths to arch file? # Vitis-AI 1.1 old_arch = "/opt/vitis_ai/compiler/arch/dpuv1/ALVEO/ALVEO.json" # Vitis-AI 1.2 - ... new_arch = "/opt/vitis_ai/compiler/arch/DPUCADX8G/ALVEO/arch.json" if os.path.exists(new_arch): arch = os.path.join(FILE_PATH, '../target/components/DPUCADX8G/arch.json') else: arch = os.path.join(FILE_PATH, '../target/components/DPUCADX8G/arch_vai_11.json') compiler = DPUCompiler(xgraph, 'dpuv1', arch, **kwargs) c_xgraph = compiler.compile() return c_xgraph pyxir.register_target('dpuv1', xgraph_dpu_optimizer, xgraph_dpu_quantizer, xgraph_dpuv1_compiler, xgraph_dpuv1_build_func) pyxir.register_op('cpu-np', 'DPU', base.get_layer(DPULayer))
from .components.DPUCZDX8G.external_quantizer_tools import xgraph_dpu_external_quantizer from .components.DPUCZDX8G.external_quantizer_tools import xgraph_dpu_external_quantizer_optimizer from .components.DPUCZDX8G.ultra96 import xgraph_dpu_ultra96_build_func from .components.DPUCZDX8G.ultra96 import xgraph_dpu_ultra96_compiler from .components.DPUCZDX8G.zcu102 import xgraph_dpu_zcu102_build_func from .components.DPUCZDX8G.zcu102 import xgraph_dpu_zcu102_compiler from .components.DPUCZDX8G.zcu104 import xgraph_dpu_zcu104_build_func from .components.DPUCZDX8G.zcu104 import xgraph_dpu_zcu104_compiler from .components.DPUCZDX8G.som import xgraph_dpu_som_build_func from .components.DPUCZDX8G.som import xgraph_dpu_som_compiler # Register target pyxir.register_target('DPUCZDX8G-ultra96', xgraph_dpu_external_quantizer_optimizer, xgraph_dpu_external_quantizer, xgraph_dpu_ultra96_compiler, xgraph_dpu_ultra96_build_func) # Register op support from .components.DPUCZDX8G import ultra96_op_support # Register target pyxir.register_target('DPUCZDX8G-zcu102', xgraph_dpu_external_quantizer_optimizer, xgraph_dpu_external_quantizer, xgraph_dpu_zcu102_compiler, xgraph_dpu_zcu102_build_func) # Register op support from .components.DPUCZDX8G import zcu102_op_support
quantizer = XGraphDefaultQuantizer(xgraph, inputs_func, work_dir=work_dir, **kwargs) q_xgraph = quantizer.quantize(subgraphs_only=False) # quantizer = XGraphMSEThresholdQuantizer(xgraph, inputs_func, # work_dir=work_dir, **kwargs) # q_xgraph = quantizer.quantize(subgraphs_only=False) return q_xgraph def qsim_xgraph_compiler(xgraph, **kwargs): # type: (XGraph) -> XGraph """ Basic xgraph quantizer """ warnings.warn("'qsim' compilation just returns the original XGraph") return xgraph pyxir.register_target('qsim-12msbs', qsim_xgraph_optimizer, qsim_xgraph_quantizer, qsim_xgraph_compiler, build_for_quantization_simulation) @pyxir.register_op_support_check('qsim-12msbs', 'All') def qsim_op_support_check(X, bXs, tXs): """ Enable all operations """ return True
# distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. """"Register DPUCAHX8H targets""" import pyxir from .components.DPUCAHX8H.common import xgraph_dpu_quantizer from .components.DPUCAHX8H.common import xgraph_dpu_optimizer from .components.DPUCAHX8H.u50 import xgraph_dpu_u50_build_func from .components.DPUCAHX8H.u50 import xgraph_dpu_u50_compiler from .components.DPUCAHX8H.u280 import xgraph_dpu_u280_build_func from .components.DPUCAHX8H.u280 import xgraph_dpu_u280_compiler # Register target pyxir.register_target('DPUCAHX8H-u50', xgraph_dpu_optimizer, xgraph_dpu_quantizer, xgraph_dpu_u50_compiler, xgraph_dpu_u50_build_func) # Register op support from .components.DPUCAHX8H import u50_op_support # Register U280 target pyxir.register_target('DPUCAHX8H-u280', xgraph_dpu_optimizer, xgraph_dpu_quantizer, xgraph_dpu_u280_compiler, xgraph_dpu_u280_build_func) # Register op support from .components.DPUCAHX8H import u280_op_support
# Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. """"Register DPUCADX8G target""" import pyxir from pyxir.runtime import base from .components.DPUCADX8G.dpu_target import xgraph_dpu_build_func from .components.DPUCADX8G.dpu_target import xgraph_dpu_optimizer from .components.DPUCADX8G.dpu_target import xgraph_dpu_compiler from .components.DPUCADX8G.dpu_target import xgraph_dpu_quantizer from .components.DPUCADX8G.dpu_target import xgraph_dpu_op_support_annotator from .components.DPUCADX8G.dpu_target import DPULayer # Register target pyxir.register_target('DPUCADX8G', xgraph_dpu_optimizer, xgraph_dpu_quantizer, xgraph_dpu_compiler, xgraph_dpu_build_func, xgraph_dpu_op_support_annotator) # Register layer pyxir.register_op('cpu-np', 'DPU', base.get_layer(DPULayer)) # Register op support from .components.DPUCADX8G import dpu_op_support
import logging from pyxir.graph.transformers import subgraph from pyxir.contrib.target.DPUCZDX8G.zcu104 import xgraph_dpu_optimizer,\ xgraph_dpu_quantizer, xgraph_dpu_zcu104_compiler logger = logging.getLogger('pyxir') def xgraph_dpuv2_zcu104_build_func(xgraph, work_dir=os.getcwd(), **kwargs): # TODO here or in optimizer, both? # DPU layers are in NHWC format because of the tensorflow # intemediate structure we use to communicate with # DECENT/DNNC return subgraph.xgraph_build_func( xgraph=xgraph, target='dpuv2-zcu104', xtype='DPU', layout='NHWC', work_dir=work_dir ) pyxir.register_target('dpuv2-zcu104', xgraph_dpu_optimizer, xgraph_dpu_quantizer, xgraph_dpu_zcu104_compiler, xgraph_dpuv2_zcu104_build_func)