Пример #1
0
def setGlbl_vars(mhs):
    global sys_clk
    global sys_reset
    global main_plb
    global lib_name
    global lib_dir_name

    lib_dir_name = "kapi_cpuhwt_v1_00_a"
    lib_name = "kapi_cpuhwt"
    instances = mhs.getPcores("plb_v34")
    xps_instances = mhs.getPcores("plb_v46")

    if len(xps_instances) > 0:
        #instances.append(xps_instances)
        if len(instances) == 0:
            instances = xps_instances
        else:
            instances.append(xps_instances)

    if len(instances) <= 0:
        sys.stderr.write("ERROR, no PLB bus in system!\n")
        sys.exit(1)

    found = 0
    for pcore in instances:
        if pcore.instance_name == "plb":
            sys.stderr.write("pcore: %s" % pcore.instance_name)
            found = 1
            main_plb = "plb"
            sys_clk = pcore.getValue("PLB_Clk")
            sys_reset = pcore.getValue("SYS_Rst")

    #if no plb with instance_name "plb" found just take the first plb instance as main_plb
    if found == 0:
        sys.stderr.write("ERROR found == 0!\n")
        main_plb = instances[0].instance_name
        sys_clk = instances[0].getValue("PLB_Clk")
        sys_reset = instances[0].getValue("SYS_Rst")
Пример #2
0
def setGlbl_vars(mhs):
    global sys_clk
    global sys_reset
    global main_plb
    global lib_name
    global lib_dir_name
    
    lib_dir_name = "kapi_cpuhwt_v1_00_a"
    lib_name = "kapi_cpuhwt"
    instances = mhs.getPcores("plb_v34")
    xps_instances = mhs.getPcores("plb_v46")
    
    if len(xps_instances) > 0:
        #instances.append(xps_instances)
        if len(instances) == 0:
            instances = xps_instances
        else:
            instances.append(xps_instances)
    
    if len(instances) <= 0:
        sys.stderr.write("ERROR, no PLB bus in system!\n")
        sys.exit(1)
           
    found = 0
    for pcore in instances:
        if pcore.instance_name == "plb":
            sys.stderr.write("pcore: %s" % pcore.instance_name) 
            found = 1
            main_plb = "plb"
            sys_clk = pcore.getValue("PLB_Clk")
            sys_reset = pcore.getValue("SYS_Rst")
    
    #if no plb with instance_name "plb" found just take the first plb instance as main_plb
    if found == 0:
        sys.stderr.write("ERROR found == 0!\n")
        main_plb = instances[0].instance_name
        sys_clk = instances[0].getValue("PLB_Clk")
        sys_reset = instances[0].getValue("SYS_Rst")  
Пример #3
0
def getBramLogicPort(mhs):
    global baseaddr  #this is used also by another function
    instance = mhs.getPcore("cpu_hwt_bram_logic")
    if instance == None:
        bram_logic = reconos.mhs.MHSPCore("cpu_hwt_bram_logic")
        bram_logic.instance_name = "CPUHWT_BRAM_LOGIC"
        bram_logic.addEntry("PARAMETER", "HW_VER", "1.00.a")

        instances = mhs.getPcores("plb_bram_if_cntlr")
        xps_instances = mhs.getPcores("xps_bram_if_cntlr")
        #instances.append(xps_instances)
        if len(instances) == 0:
            instances = xps_instances
        else:
            instances.append(xps_instances)

        if len(instances) > 0:
            bus_interface_porta = ""
            found = 0
            for bc in instances:
                if (bc.getValue("C_HIGHADDR")
                        == "0xffffffff") or (bc.getValue("C_HIGHADDR")
                                             == "0xFFFFFFFF"):
                    #this is the right bram_ctrl
                    #now get Value of PortB and start searching for right BRAM_BLOCK
                    found = 1
                    bus_interface_porta = bc.getValue("PORTA")
                    baseaddr = bc.getValue("C_BASEADDR")
                    break

            if found == 0:
                sys.stderr.write(
                    "ERROR, no BRAM-CTRL which ends at Address 0xFFFFFFFF!\n")
                sys.exit(1)
            #if bramctrl was found check if via baseaddr if the bramsize is big enough
            #it should be > 16kb because we leave 8kb for ecos
            bram_size = 0xffffffff - int(baseaddr, 16)
            if bram_size < 0x3fff:
                sys.stderr.write(
                    "Size of bram_ctrl with C_HIGHADDR=0xFFFFFFFF is too small. It has to be minimum 16kb!!!!\n"
                )
                sys.exit(1)
            #now manipulate the eCos linkerscript (target.ld) to reduce the bram-space used by eCos
            #this is done because the eCos executable is loaded last and if the whole bramspace is added in target.ld
            #all the boot0 sections of the CPU-HW-Threads will be zeroed

            #get all BRAM_BLOCK instances
            instances = mhs.getPcores("bram_block")

            if len(instances) <= 0:
                sys.stderr.write("ERROR, no BRAM-BLOCKS in system!\n")
                sys.exit(1)

            #search all instances for the right bram_block (the bram which is connected to the right bram_ctrl)
            for bb in instances:
                if bb.getValue("PORTA") == bus_interface_porta:
                    #set PORTB to bram_ctrl_logic
                    ##check if PORTB is already used
                    portb_val = bb.getValue("PORTB")
                    if portb_val != None:
                        sys.stderr.write("ERROR, PORTB of %s is not free! \n" %
                                         bb.instance_name)
                        sys.exit(1)
                    #connect cpu_hwt_bram_logic with bram_block
                    bb.addEntry("BUS_INTERFACE", "PORTB",
                                "CPU_HWT_BRAM_LOGIC_PORT")
                    bram_logic.addEntry("BUS_INTERFACE", "PORTB",
                                        "CPU_HWT_BRAM_LOGIC_PORT")
                    #now connect clk and rst
                    bram_logic.addEntry("PORT", "clk", sys_clk)
                    bram_logic.addEntry("PORT", "reset", sys_reset)
                    #This is the first instantiation of the cpu_hwt_bram_logic so we return the CPU0 Port
                    ret_val = "BRAM_LOGIC_CPU_PORT_0"
                    bram_logic.addEntry("BUS_INTERFACE", "CPU0", ret_val)
                    #Because this is the first CPUHWT the library has to be linked to the edk dir
                    set_cpuhwt_lib()
                    break

            mhs.pcores.append(bram_logic)
            return ret_val

        else:
            sys.stderr.write("ERROR, no BRAM-CTRL Instance!\n")
            sys.exit(1)

    else:
        sys.stderr.write(
            "ERROR. This toolchain can only manage 1 CPU-HW-Thread!\n")
        sys.exit(1)
Пример #4
0
    os.mkdir(pcore_name)
    open(readme_file, "w").write(readme_text)

    #Now check which cpu_type and begin scanning/modifiing the mhs file
    mhs_file = "../../edk-static/system.mhs"
    mhs_new = "../../edk-static/system.mhsnew"
    mss_file = "../../edk-static/system.mss"
    mss_new = "../../edk-static/system.mssnew"
    mhs = reconos.mhs.MHS(mhs_file)
    mss = reconos.mss.MSS(mss_file)
    #before scanning, set the global vars
    setGlbl_vars(mhs)

    if cpuhwt_type == "PPC405":
        if (platform == "virtex2"):
            ppc_instances = mhs.getPcores("ppc405")
        elif (platform == "virtex4"):
            ppc_instances = mhs.getPcores("ppc405_virtex4")

        if (len(ppc_instances)) <= 1:
            #the toolchain requires that the reference design has already instantiated the processors
            sys.stderr.write("Only one PowerPC in system!\n")
            sys.exit(1)
        else:
            found = 0
            ppc_core = None
            #search for ppc instance which is not used
            for pcore in ppc_instances:
                #ppc405_0 is the ecos cpu
                if pcore.instance_name != "ppc405_0":
                    #make a simple check if ppc is already used (if the IPLB is connected the PPC could be in use)
Пример #5
0
def getBramLogicPort(mhs):
    global baseaddr  #this is used also by another function
    instance = mhs.getPcore("cpu_hwt_bram_logic")
    if instance == None:
        bram_logic = reconos.mhs.MHSPCore("cpu_hwt_bram_logic")
        bram_logic.instance_name = "CPUHWT_BRAM_LOGIC"
        bram_logic.addEntry("PARAMETER","HW_VER","1.00.a")
        
        instances = mhs.getPcores("plb_bram_if_cntlr")
        xps_instances = mhs.getPcores("xps_bram_if_cntlr")
        #instances.append(xps_instances)
        if len(instances) == 0:
            instances = xps_instances
        else:
            instances.append(xps_instances)
    
        if len(instances) > 0:
            bus_interface_porta = ""
            found = 0
            for bc in instances:
                if (bc.getValue("C_HIGHADDR") == "0xffffffff") or (bc.getValue("C_HIGHADDR") == "0xFFFFFFFF"):
                    #this is the right bram_ctrl
                    #now get Value of PortB and start searching for right BRAM_BLOCK
                    found = 1       
                    bus_interface_porta = bc.getValue("PORTA")
                    baseaddr = bc.getValue("C_BASEADDR")
                    break
            
            if found == 0:
                sys.stderr.write("ERROR, no BRAM-CTRL which ends at Address 0xFFFFFFFF!\n")
                sys.exit(1)
            #if bramctrl was found check if via baseaddr if the bramsize is big enough
            #it should be > 16kb because we leave 8kb for ecos
            bram_size = 0xffffffff - int(baseaddr, 16)
            if bram_size < 0x3fff:
                sys.stderr.write("Size of bram_ctrl with C_HIGHADDR=0xFFFFFFFF is too small. It has to be minimum 16kb!!!!\n")
                sys.exit(1) 
            #now manipulate the eCos linkerscript (target.ld) to reduce the bram-space used by eCos
            #this is done because the eCos executable is loaded last and if the whole bramspace is added in target.ld
            #all the boot0 sections of the CPU-HW-Threads will be zeroed
            
            #get all BRAM_BLOCK instances
            instances = mhs.getPcores("bram_block")
            
            if len(instances) <= 0:
               sys.stderr.write("ERROR, no BRAM-BLOCKS in system!\n")
               sys.exit(1) 
           
            #search all instances for the right bram_block (the bram which is connected to the right bram_ctrl)
            for bb in instances:
                if bb.getValue("PORTA") == bus_interface_porta:
                    #set PORTB to bram_ctrl_logic
                    ##check if PORTB is already used
                    portb_val = bb.getValue("PORTB")
                    if portb_val != None:
                        sys.stderr.write("ERROR, PORTB of %s is not free! \n" % bb.instance_name)
                        sys.exit(1)
                    #connect cpu_hwt_bram_logic with bram_block    
                    bb.addEntry("BUS_INTERFACE", "PORTB", "CPU_HWT_BRAM_LOGIC_PORT")
                    bram_logic.addEntry("BUS_INTERFACE", "PORTB", "CPU_HWT_BRAM_LOGIC_PORT")
                    #now connect clk and rst
                    bram_logic.addEntry("PORT", "clk", sys_clk)
                    bram_logic.addEntry("PORT", "reset", sys_reset)
                    #This is the first instantiation of the cpu_hwt_bram_logic so we return the CPU0 Port
                    ret_val = "BRAM_LOGIC_CPU_PORT_0"
                    bram_logic.addEntry("BUS_INTERFACE", "CPU0", ret_val)
                    #Because this is the first CPUHWT the library has to be linked to the edk dir
                    set_cpuhwt_lib()
                    break
            
            mhs.pcores.append(bram_logic)
            return ret_val
               
        else:
            sys.stderr.write("ERROR, no BRAM-CTRL Instance!\n")
            sys.exit(1)
     
    else:
       sys.stderr.write("ERROR. This toolchain can only manage 1 CPU-HW-Thread!\n")  
       sys.exit(1)
Пример #6
0
 os.mkdir(pcore_name)
 open(readme_file, "w").write(readme_text)
 
 #Now check which cpu_type and begin scanning/modifiing the mhs file
 mhs_file = "../../edk-static/system.mhs"
 mhs_new  = "../../edk-static/system.mhsnew"
 mss_file = "../../edk-static/system.mss"
 mss_new  = "../../edk-static/system.mssnew"
 mhs = reconos.mhs.MHS(mhs_file)
 mss = reconos.mss.MSS(mss_file)
 #before scanning, set the global vars
 setGlbl_vars(mhs)
 
 if cpuhwt_type == "PPC405":
     if (platform == "virtex2"):
         ppc_instances = mhs.getPcores("ppc405")
     elif (platform =="virtex4"):
         ppc_instances = mhs.getPcores("ppc405_virtex4")
     
     if (len(ppc_instances)) <= 1:
         #the toolchain requires that the reference design has already instantiated the processors
         sys.stderr.write("Only one PowerPC in system!\n")
         sys.exit(1)
     else:
         found = 0
         ppc_core = None
         #search for ppc instance which is not used
         for pcore in ppc_instances:
             #ppc405_0 is the ecos cpu
             if pcore.instance_name != "ppc405_0":
                 #make a simple check if ppc is already used (if the IPLB is connected the PPC could be in use)