def displayReg(reg, option=None):
address = reg.real_address
if 'r' not in reg.permission:
return 'No read permission!'
value = rReg(parseInt(address))
if parseInt(value) == 0xdeaddead:
if option == 'hexbin':
return hex(
address).rstrip('L') + ' ' + reg.permission + '\t' + tabPad(
reg.name, 7) + 'Bus Error'
else:
return hex(
address).rstrip('L') + ' ' + reg.permission + '\t' + tabPad(
reg.name, 7) + 'Bus Error'
if reg.mask is not None:
shift_amount = 0
for bit in reversed('{0:b}'.format(reg.mask)):
if bit == '0': shift_amount += 1
else: break
final_value = (parseInt(str(reg.mask))
& parseInt(value)) >> shift_amount
else:
final_value = value
final_int = parseInt(final_value)
if option == 'hexbin':
return hex(address).rstrip('L') + ' ' + reg.permission + '\t' + tabPad(
reg.name, 7) + '{0:#010x}'.format(
final_int) + ' = ' + '{0:032b}'.format(final_int)
else:
return hex(address).rstrip('L') + ' ' + reg.permission + '\t' + tabPad(
reg.name, 7) + '{0:#010x}'.format(final_int)
def writeReg(reg, value):
address = reg.real_address
if 'w' not in reg.permission:
return 'No write permission!'
# Apply Mask if applicable
if reg.mask is not None:
shift_amount = 0
for bit in reversed('{0:b}'.format(reg.mask)):
if bit == '0': shift_amount += 1
else: break
shifted_value = value << shift_amount
for i in range(10):
initial_value = readAddress(address)
try:
initial_value = parseInt(initial_value)
except ValueError:
return 'Error reading initial value: ' + str(initial_value)
if initial_value == 0xdeaddead:
print "Writing masked reg %s : Error while reading, retry attempt (%s)" % (
reg.name, i)
sleep(0.1)
continue
else:
break
if initial_value == 0xdeaddead:
print "Writing masked reg %s failed. Exiting..." % (reg.name)
final_value = (shifted_value & reg.mask) | (initial_value & ~reg.mask)
else:
final_value = value
output = wReg(parseInt(address), parseInt(final_value))
if output != final_value:
print "Writing masked reg %s failed. Exiting..." % (reg.name)
print "wReg output %s" % (output)
return str('{0:#010x}'.format(final_value)).rstrip('L') + '(' + str(
value) + ')\twritten to ' + reg.name
def checkStatus(ohList):
rxReady = parseInt(readReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.STATUS.READY')))
criticalError = parseInt(readReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.STATUS.CRITICAL_ERROR')))
statusGood = True
for i in ohList:
if not check_bit(rxReady, i):
printRed("OH #%d is not ready: RX ready = %d, critical error = %d" % (i, (rxReady >> i) & 0x1, (criticalError >> i) & 0x1))
statusGood = False
return statusGood
def readReg(reg):
address = reg.real_address
if 'r' not in reg.permission:
return 'No read permission!'
value = rReg(parseInt(address))
if parseInt(value) == 0xdeaddead:
#return 'Bus Error'
return '{0:#010x}'.format(0xdeaddead)
if reg.mask is not None:
shift_amount = 0
for bit in reversed('{0:b}'.format(reg.mask)):
if bit == '0': shift_amount += 1
else: break
final_value = (parseInt(str(reg.mask))
& parseInt(value)) >> shift_amount
else:
final_value = value
final_int = parseInt(str(final_value))
return '{0:#010x}'.format(final_int)
def sendScaCommand(ohList, sca_channel, sca_command, data_length, data, doRead):
#print('fake send: channel ' + hex(sca_channel) + ', command ' + hex(sca_command) + ', length ' + hex(data_length) + ', data ' + hex(data) + ', doRead ' + str(doRead))
#return
d = data
writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.MANUAL_CONTROL.SCA_CMD.SCA_CMD_CHANNEL'), sca_channel)
writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.MANUAL_CONTROL.SCA_CMD.SCA_CMD_COMMAND'), sca_command)
writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.MANUAL_CONTROL.SCA_CMD.SCA_CMD_LENGTH'), data_length)
writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.MANUAL_CONTROL.SCA_CMD.SCA_CMD_DATA'), d)
writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.MANUAL_CONTROL.SCA_CMD.SCA_CMD_EXECUTE'), 0x1)
reply = []
if doRead:
for i in ohList:
reply.append(parseInt(readReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.MANUAL_CONTROL.SCA_REPLY_OH%d.SCA_RPY_DATA' % i))))
return reply
def readRawAddress(raw_address):
try:
address = (parseInt(raw_address) << 2) + 0x64000000
return readAddress(address)
except:
return 'Error reading address. (rw_reg)'
def readAddress(address):
output = rReg(address)
return '{0:#010x}'.format(parseInt(str(output)))
def jtagCommand(restoreIdle, ir, irLen, dr, drLen, drReadOhList):
totalLen = 0
if ir is not None:
totalLen += irLen + 6 # instruction register length plus 6 TMS bits required to get to the IR shift state and back to IDLE
if dr is not None:
totalLen += drLen + 5 # data register length plus 5 TMS bits required to get to the DR shift state and back to IDLE
if restoreIdle:
totalLen += 6
if totalLen > 128:
raise ValueError(
'JTAG command request needs more than 128 bits -- not possible. Please break up your command into smaller pieces.'
)
tms = 0
tdo = 0
len = 0
readIdx = 0
if restoreIdle:
tms = 0b011111
len = 6
if ir is not None:
tms |= 0b0011 << len # go to IR SHIFT state
len += 4
tdo |= ir << len
tms |= 0b1 << (irLen - 1 + len) # exit IR shift
len += irLen
tms |= 0b01 << len # update IR and go to IDLE
len += 2
if dr is not None:
tms |= 0b001 << len # go to DR SHIFT state
len += 3
readIdx = len
tdo |= dr << len
tms |= 0b1 << (drLen - 1 + len) # exit DR shift
len += drLen
tms |= 0b01 << len # update DR and go to IDLE
len += 2
debug('Length = ' + str(len))
debug('TMS = ' + binary(tms, len))
debug('TDO = ' + binary(tdo, len))
debug('Read start index = ' + str(readIdx))
debugCyan('Setting command length = ' + str(len))
fw_len = len if len < 128 else 0 # in firmware 0 means 128 bits
#writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.NUM_BITS'), fw_len)
wReg(ADDR_JTAG_LENGTH, fw_len)
# ================= SENDING LENGTH COMMAND JUST FOR TEST!! ===================
#debugCyan('Setting config registers: bit number = ' + hex(fw_len))
#sendScaCommand(0x13, 0x80, 0x4, 0xc00 | (fw_len << 24), False) # TX falling edge, shift LSB first, and set length
# ============================================================================
#raw_input("press any key to send tms and tdo")
debugCyan('Setting TMS 0 = ' + binary(tms & 0xffffffff, 32))
#writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.TMS'), tms0)
wReg(ADDR_JTAG_TMS, tms & 0xffffffff)
debugCyan('Setting TDO 0 = ' + binary(tdo & 0xffffffff, 32))
#writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.TDO'), tdo0)
wReg(ADDR_JTAG_TDO, tdo & 0xffffffff)
if len > 32:
tms = tms >> 32
debugCyan('Setting TMS 1 = ' + binary(tms & 0xffffffff, 32))
#writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.TMS'), tms1)
wReg(ADDR_JTAG_TMS, tms & 0xffffffff)
#raw_input("press any key to send the last TDO")
tdo = tdo >> 32
debugCyan('Setting TDO 1 = ' + binary(tdo & 0xffffffff, 32))
#writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.TDO'), tdo1)
wReg(ADDR_JTAG_TDO, tdo & 0xffffffff)
if len > 64:
tms = tms >> 32
debugCyan('Setting TMS 2 = ' + binary(tms & 0xffffffff, 32))
#writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.TMS'), tms2)
wReg(ADDR_JTAG_TMS, tms & 0xffffffff)
tdo = tdo >> 32
debugCyan('Setting TDO 2 = ' + binary(tdo & 0xffffffff, 32))
#writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.TDO'), tdo2)
wReg(ADDR_JTAG_TDO, tdo & 0xffffffff)
if len > 96:
tms = tms >> 32
debugCyan('Setting TMS 3 = ' + binary(tms & 0xffffffff, 32))
#writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.TMS'), tms3)
wReg(ADDR_JTAG_TMS, tms & 0xffffffff)
tdo = tdo >> 32
debugCyan('Setting TDO 3 = ' + binary(tdo & 0xffffffff, 32))
#writeReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.TDO'), tdo3)
wReg(ADDR_JTAG_TDO, tdo & 0xffffffff)
# ================= SENDING JTAG GO COMMAND JUST FOR TEST!! ===================
#debugCyan('JTAG GO!')
#sendScaCommand(0x13, 0xa2, 0x1, 0x0, False)
# ============================================================================
#raw_input("Press any key to read TDI...")
readValues = {}
if drReadOhList == False:
return readValues
for i in drReadOhList:
debugCyan('Read TDI 0')
tdi = parseInt(
readReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.TDI_OH%d' % i)))
#tdi0_fast = parseInt(rReg(parseInt(ADDR_JTAG_TDI)))
#print('normal tdi read = ' + hex(tdi0) + ', fast C tdi read = ' + hex(tdi0_fast) + ', parsed = ' + '{0:#010x}'.format(tdi0_fast))
debug('tdi = ' + hex(tdi))
if len > 32:
debugCyan('Read TDI 1')
tdi1 = parseInt(
readReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.TDI_OH%d' % i)))
tdi |= tdi1 << 32
debug('tdi1 = ' + hex(tdi1))
debug('tdi = ' + hex(tdi))
if len > 64:
debugCyan('Read TDI 2')
tdi2 = parseInt(
readReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.TDI_OH%d' % i)))
tdi |= tdi2 << 64
debug('tdi2 = ' + hex(tdi2))
debug('tdi = ' + hex(tdi))
if len > 96:
debugCyan('Read TDI 3')
tdi3 = parseInt(
readReg(getNode('GEM_AMC.SLOW_CONTROL.SCA.JTAG.TDI_OH%d' % i)))
tdi |= tdi3 << 96
debug('tdi3 = ' + hex(tdi3))
debug('tdi = ' + hex(tdi))
readValue = (tdi >> readIdx) & (0xffffffffffffffffffffffffffffffff >>
(128 - drLen))
readValues[i] = readValue
debug('Read pos = ' + str(readIdx))
debug('Read = ' + hex(readValue))
return readValues
