def MOD(i): (l, y, z) = (datafile.block[i].out, datafile.block[i].op1, datafile.block[i].op2) register.storereg('edx') datafile.blockout.append("xor edx, edx") datafile.lineno = datafile.lineno + 1 try : int(z) datafile.zprime = z reg = register.emptyregister(i,['eax', 'edx']) datafile.blockout.append('mov ' + reg + ", " + z) datafile.lineno = datafile.lineno + 1 datafile.zprime = reg except : if datafile.addressdescriptor[z] == 'eax': register.storereg(z) register.getz(z) pass register.getreg(l, y, i, 'eax') try : int(y) datafile.yprime = y except : pass register.gety(y) datafile.blockout.append("idiv " + register.mem(datafile.zprime)) datafile.lineno = datafile.lineno + 1 datafile.L = 'edx' #since the remainder is store in edx register.update(l) register_allocator.freereg(y, i) register_allocator.freereg(z, i)
def DIV(i): (l, y, z) = (datafile.block[i].out, datafile.block[i].op1, datafile.block[i].op2) register.storereg('edx') datafile.blockout.append("xor %edx, %edx") datafile.lineno = datafile.lineno + 1 try : int(z) reg = register.emptyregister(i,['edx', 'eax']) datafile.blockout.append('mov $' + z + ", %" + reg) datafile.lineno = datafile.lineno + 1 datafile.zprime = reg except : if datafile.addressdescriptor[z] == 'eax': register.storereg(z) register.getz(z) pass register.getreg(l, y, i, 'eax') try : int(y) datafile.yprime = y except : pass register.gety(y) datafile.blockout.append("idivl " + register.mem(datafile.zprime)) datafile.lineno = datafile.lineno + 1 register.UpdateAddressDescriptor(l) register.freereg(y, i) register.freereg(z, i)
def ADD(i): (y, z, l) = (datafile.block[i].op1, datafile.block[i].op2, datafile.block[i].out) #check if z is constant or not if not get the momloc or register if it is already in register since op r_i , r_j is similar to op r_i , M print y,", ", z, ", ", l ,"these are y and l in add function" try : int(z) datafile.zprime = z except : register.getz(z) pass #get the register for L to store the output of the operation register.getreg(l, y, i) # print datafile.L , "Hello" try : int(y) datafile.yprime = y except : pass register.gety(y) datafile.blockout.append("addl " + register.mem(datafile.zprime) + ", " + register.mem(datafile.L)) # datafile.blockout.append("lineno" + str(datafile.lineno)) datafile.lineno = datafile.lineno + 1 register.UpdateAddressDescriptor(l) register.freereg(y, i) register.freereg(z, i)
def ASSIGN(i): (y,l) = (datafile.block[i].op2,datafile.block[i].out) register.getreg(l,y,i) try : int(y) datafile.yprime = y except : pass register.gety(y) register.UpdateAddressDescriptor(l) register.freereg(y, i)
def ADD(i): (y, z, l) = (datafile.block[i].op1, datafile.block[i].op2, datafile.block[i].out) try : int(z) datafile.zprime = z except : register.getz(z) pass register.getreg(l, y, i) try : int(y) datafile.yprime = y except : pass register.gety(y) datafile.blockout.append("add " + register.mem(datafile.L) + ", "+register.mem(datafile.zprime) ) datafile.lineno = datafile.lineno + 1 register.UpdateAddressDescriptor(l) register.freereg(y, i) register.freereg(z, i)
def XOR(i): (y, z, l) = (datafile.block[i].op1, datafile.block[i].op2, datafile.block[i].out) #check if z is constant or not if not get the momloc or register if it is already in register since op r_i , r_j is similar to op r_i , M try : int(z) datafile.zprime = z except : register.getz(z) pass #get the register for L to store the output of the operation register.getreg(l, y, i) try : int(y) datafile.yprime = y except : pass register.gety(y) datafile.blockout.append("xor " + register.mem(datafile.L) + ", " + register.mem(datafile.zprime) ) datafile.lineno = datafile.lineno + 1 register.UpdateAddressDescriptor(l) register.freereg(y, i) register.freereg(z, i)