def led_blinker_top(clock, reset, leds, buttons):
glbl = Global(clock, reset)
csrbus = Barebone()
dbtns = Signal(buttons.val)
led_inst = led_blinker(glbl, csrbus, leds)
dbn_inst = button_debounce(glbl, buttons, dbtns)
btn_inst = button_controller(glbl, csrbus, dbtns)
# above all the components have been added, now build the
# register file (figures out addresses, etc) and then get
# the memory-mapped bus interconnect
csrbus.regfile_build()
bus_inst = csrbus.interconnect()
return myhdl.instances()
def m_btn_led_mm(clock, reset, leds, btns, bus_type='W'):
""" A toy example to demostrate bus agnosticism
This example instantiates a memory-map controller and a
memory-map peripheral. This example shows how the
controllers and peripherals can be passed the memmap
interface. The passing of the interface allows the
modules (components) to be bus agnostic.
This example solves a simple task in a complicated manner
to show the point. When a button press is detected a
bus cycle is generated to write the "flash" pattern to
the LED peripheral.
Note: for easy FPGA bit-stream generation the port names
match the board names defined in the *gizflo* board definitions.
"""
glbl = Global(clock=clock, reset=reset)
if bus_type == 'B':
regbus = Barebone(glbl, data_width=8, address_width=16)
elif bus_type == 'W':
regbus = Wishbone(glbl, data_width=8, address_width=16)
elif bus_type == 'A':
regbus = AvalonMM(glbl, data_width=8, address_width=16)
#elif bus_type == 'X':
# regbus = AXI4Lite(glbl, data_wdith=8, address_width=16)
else:
raise Exception("Invalid bus type {}".format(bus_type))
gbtn = button_controller(glbl, regbus, btns) # memmap controller
gled = led_peripheral(glbl, regbus, leds) # memmap peripheral
gmap = regbus.interconnect() # bus combiner
print(vars(regbus.regfiles['LED_000']))
return gbtn, gled, gmap
def m_btn_led_mm(clock, reset, leds, btns, bus_type='W'):
""" A toy example to demostrate bus agnosticism
This example instantiates a memory-map controller and a
memory-map peripheral. This example shows how the
controllers and peripherals can be passed the memmap
interface. The passing of the interface allows the
modules (components) to be bus agnostic.
This example solves a simple task in a complicated manner
to show the point. When a button press is detected a
bus cycle is generated to write the "flash" pattern to
the LED peripheral.
Note: for easy FPGA bit-stream generation the port names
match the board names defined in the *gizflo* board definitions.
"""
glbl = Global(clock=clock, reset=reset)
if bus_type == 'B':
regbus = Barebone(glbl, data_width=8, address_width=16)
elif bus_type == 'W':
regbus = Wishbone(glbl, data_width=8, address_width=16)
elif bus_type == 'A':
regbus = AvalonMM(glbl, data_width=8, address_width=16)
#elif bus_type == 'X':
# regbus = AXI4Lite(glbl, data_wdith=8, address_width=16)
else:
raise Exception("Invalid bus type {}".format(bus_type))
gbtn = button_controller(glbl, regbus, btns) # memmap controller
gled = led_peripheral(glbl, regbus, leds) # memmap peripheral
gmap = regbus.interconnect() # bus combiner
print(vars(regbus.regfiles['LED_000']))
return gbtn, gled, gmap