def run(args, builder, build_kwargs, target_name):
# Generate files in the build directory
configure_generated_files(builder, args, target_name)
# Build & run
if not args.sim: # hardware
builder.build(**build_kwargs, run=args.build)
else: # simulation
sim_kwargs = get_sim_kwargs(args)
builder.build(**build_kwargs, run=args.build, **sim_kwargs)
if args.docs:
doc.generate_docs(builder.soc,
base_dir="build/documentation",
project_name="LiteX Row Hammer Tester",
author="Antmicro")
if args.load:
prog = builder.soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir,
builder.soc.build_name + ".bit"))
if args.load_bios:
assert args.rw_bios_mem, 'BIOS memory must be writible'
from rowhammer_tester.scripts.utils import RemoteClient, memwrite
wb = RemoteClient()
wb.open()
from litex.soc.integration.common import get_mem_data
bios_bin = os.path.join(builder.software_dir, "bios", "bios.bin")
rom_data = get_mem_data(bios_bin, "little")
print(
f"Loading BIOS from: {bios_bin} starting at 0x{wb.mems.rom.base:08x} ..."
)
print('Stopping CPU')
wb.regs.ctrl_reset.write(0b10) # cpu_rst
memwrite(wb, rom_data, base=wb.mems.rom.base)
wb.read(wb.mems.rom.base)
print('Rebooting CPU')
wb.regs.ctrl_reset.write(0)
wb.close()
if args.flash:
prog = builder.soc.platform.create_programmer()
prog.flash(
0,
os.path.join(builder.gateware_dir,
builder.soc.build_name + ".bin"))
if args.test_modules:
hw_memset(wb, 0x0, mem_range, [0xffffffff], args.dbg)
# --------------------------- Introduce error ------------------------
rng = random.Random(datetime.now())
offsets = []
for i, n in enumerate(range(0, 5000)):
print('Generated {:d} offsets'.format(i), end='\r')
offset = rng.randrange(0x0, mem_range - 4)
offset &= ~0b11 # must be 32-bit aligned
if offset // nbytes not in offsets:
offsets.append(offset // nbytes)
if args.dbg:
print('dbg: offset: ' + str(offset))
wb.write(mem_base + offset,
wb.read(mem_base + offset) ^ 0x000010000)
print()
# Corner case
#offsets.append((mem_range - 4)//16)
#wb.write(mem_base + mem_range - 4, wb.read(mem_base + mem_range - 4) ^ 0x00100000)
#if args.dbg:
# print('dbg: 0x{:08x}: 0x{:08x}'.format(mem_base + mem_range - 4, wb.read(mem_base + mem_range - 4)))
print('dbg: offsets: {:d}'.format(len(offsets)))
# --------------------------------------------------------------------
start_time = time.time()
errors = hw_memtest(wb, 0x0, mem_range, [0xffffffff], args.dbg)
end_time = time.time()
wb.regs.writer_start.write(0)
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 0 * 4, 16)]))
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 4 * 4 * 4, 16)]))
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 8 * 4 * 4, 16)]))
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 12 * 4 * 4, 16)]))
# FIXME: random
#off = 67108864 - 100
#wb.write(0x40000000 + off * 4, 0xffffefff)
# --------------------------------------------------------------------
offset = random.Random(datetime.now()).randrange(
0x0, 256 * 1024 * 1024 - 32) # FIXME: Check corner case
print('offset: ' + str(offset) + ', expecting: ' +
str((offset // 16) * 16))
wb.write(0x40000000 + offset, wb.read(0x40000000 + offset) ^ 0x000010000)
# --------------------------------------------------------------------
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 0 * 4, 16)]))
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 4 * 4 * 4, 16)]))
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 8 * 4 * 4, 16)]))
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 12 * 4 * 4, 16)]))
wb.regs.reader_start.write(0)
wb.regs.reader_reset.write(1)
time.sleep(10000 / 1e6)
wb.regs.reader_reset.write(0)
# Expected pattern
wb.write(0x30000000, 0xffffffff) # patttern
wb.write(0x31000000, 0xffffffff) # patttern