Пример #1
0
                             simOptions, tdc_width, dcoName, designName, Fref,
                             Kp, outputDir)

tapeout_mode = 0

if outMode == 'macro' or outMode == 'full':
    #--------------------------------------------------------
    # generate Feed Forward DCO
    #--------------------------------------------------------
    dco_bleach = 1  # test switch
    dco_synth = 1
    dco_apr = 1
    W_dco, H_dco = run_digital_flow.dco_flow(
        pvtFormatDir, dco_flowDir, dcoName, dco_bleach, Ndrv, Ncc, Nfc, Nstg,
        W_CC, H_CC, W_FC, H_FC, dco_synth, dco_apr, verilogSrcDir, platform,
        edge_sel, buf_small, buf_big, bufz, min_p_rng_l, min_p_str_l, p_rng_w,
        p_rng_s, p2_rng_w, p2_rng_s, max_r_l, cust_place, single_ended,
        FC_half, CC_stack, dco_CC_name, dco_FC_name, cp_version, welltap_dim,
        welltap_xc, ND, outputDir, synthTool, track)
    #--------------------------------------------------------
    # generate output buffer, divider
    #--------------------------------------------------------
    buf_bleach = 1
    buf_design = 1
    buf_lvs = 0
    if outbuff_div == 1:
        run_digital_flow.outbuff_div_flow(pvtFormatDir, outbuff_div_flowDir,
                                          bufName, platform, buf_bleach,
                                          buf_design)
        if buf_lvs == 1:
            run_digital_flow.buf_custom_lvs(calibreRulesDir,
Пример #2
0
bufName = 'outbuff_div'
run_digital_flow.pll_verilog_gen(outMode, designName, absGenDir, outputDir,
                                 formatDir, pll_flowDir, Ndrv, Ncc, Nfc, Nstg,
                                 verilogSrcDir, buf_small, bufz, buf_big,
                                 edge_sel, dcoName, platform)

if outMode == 'macro' or outMode == 'full':
    #--------------------------------------------------------
    # generate Feed Forward DCO
    #--------------------------------------------------------
    dco_bleach = 0  # test switch
    dco_synth = 1
    dco_apr = 1
    W_dco, H_dco = run_digital_flow.dco_flow(
        pvtFormatDir, dco_flowDir, dcoName, dco_bleach, Ndrv, Ncc, Nfc, Nstg,
        W_CC, H_CC, W_FC, H_FC, dco_synth, dco_apr, verilogSrcDir, platform,
        edge_sel, buf_small, buf_big, bufz, min_p_rng_l, min_p_str_l, p_rng_w,
        p_rng_s, p2_rng_w, p2_rng_s, max_r_l)
    #--------------------------------------------------------
    # generate output buffer, divider
    #--------------------------------------------------------
    buf_bleach = 1
    buf_design = 1
    buf_lvs = 1
    if outbuff_div == 1:
        run_digital_flow.outbuff_div_flow(pvtFormatDir, outbuff_div_flowDir,
                                          bufName, platform, buf_bleach,
                                          buf_design)
        if buf_lvs == 1:
            run_digital_flow.buf_custom_lvs(calibreRulesDir,
                                            outbuff_div_flowDir, extDir,