def test_arbitrator_count(self):
"""gets the module tags and detects if there is any arbitrator hosts"""
filename = saputils.find_rtl_file_location("wb_gpio.v")
tags = saputils.get_module_tags(filename, debug=self.dbg)
self.assertEqual(len(tags["arbitrator_masters"]), 0)
filename = saputils.find_rtl_file_location("wb_console.v")
tags = saputils.get_module_tags(filename, debug=self.dbg)
self.assertEqual(len(tags["arbitrator_masters"]), 2)
def test_arbitrator_count(self):
"""gets the module tags and detects if there is any arbitrator hosts"""
filename = saputils.find_rtl_file_location("wb_gpio.v")
tags = saputils.get_module_tags(filename, debug=self.dbg)
self.assertEqual(len(tags["arbitrator_masters"]), 0)
filename = saputils.find_rtl_file_location("wb_console.v")
tags = saputils.get_module_tags(filename, debug=self.dbg)
self.assertEqual(len(tags["arbitrator_masters"]), 2)
def test_generate_buffer_slave(self):
absfilepath = saputils.find_rtl_file_location("wb_gpio.v")
slave_keywords = [
"DRT_ID",
"DRT_FLAGS",
"DRT_SIZE"
]
mtags = saputils.get_module_tags(filename = absfilepath, bus="wishbone", keywords = slave_keywords)
self.gen.wires = [
"clk",
"rst"
]
tags = {}
try:
filename = os.getenv("SAPLIB_BASE") + "/example_project/mem_example.json"
filein = open(filename)
filestr = filein.read()
tags = json.loads(filestr)
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
self.gen.tags = tags
result = self.gen.generate_buffer(name="wbs", index=0, module_tags = mtags)
buf = result
#print "out:\n" + buf
self.assertEqual(len(buf) > 0, True)
def test_generate_buffer_slave(self):
absfilepath = saputils.find_rtl_file_location("wb_gpio.v")
slave_keywords = ["DRT_ID", "DRT_FLAGS", "DRT_SIZE"]
mtags = saputils.get_module_tags(filename=absfilepath,
bus="wishbone",
keywords=slave_keywords)
self.gen.wires = ["clk", "rst"]
tags = {}
try:
filename = os.getenv(
"SAPLIB_BASE") + "/example_project/mem_example.json"
filein = open(filename)
filestr = filein.read()
tags = json.loads(filestr)
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
self.gen.tags = tags
result = self.gen.generate_buffer(name="wbs",
index=0,
module_tags=mtags)
buf = result
#print "out:\n" + buf
self.assertEqual(len(buf) > 0, True)
def test_get_number_of_arbitrator_hosts(self): #the first test should fail file_name = "wb_gpio.v" file_name = saputils.find_rtl_file_location(file_name) m_tags = saputils.get_module_tags(file_name, "wishbone") result = saparbitrator.get_number_of_arbitrator_hosts(m_tags, debug = self.dbg) self.assertEqual(len(result), 0) #the second test should pass file_name = "wb_console.v" file_name = saputils.find_rtl_file_location(file_name) m_tags = saputils.get_module_tags(file_name, "wishbone") result = saparbitrator.get_number_of_arbitrator_hosts(m_tags, debug = self.dbg) self.assertEqual(len(result), 2)
def test_generate_buffer_ftdi_io_handler(self):
absfilepath = saputils.find_rtl_file_location("ft_host_interface.v")
slave_keywords = ["DRT_ID", "DRT_FLAGS", "DRT_SIZE"]
mtags = saputils.get_module_tags(filename=absfilepath,
bus="wishbone",
keywords=slave_keywords)
self.gen.wires = ["clk", "rst"]
tags = {}
try:
filename = os.getenv(
"SAPLIB_BASE") + "/example_project/syc1_proto_gpio_mem.json"
filein = open(filename)
filestr = filein.read()
tags = json.loads(filestr)
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
self.gen.tags = tags
self.gen.bindings = self.gen.tags["bind"]
#self.gen.bindings = self.gen.tags["CONSTRAINTS"]["bind"]
result = self.gen.generate_buffer(name="uio",
module_tags=mtags,
io_module=True,
debug=self.dbg)
buf = result
# print "out:\n" + buf
self.assertEqual(len(buf) > 0, True)
def move_slave(self, slave_name = None,
from_slave_type = SlaveType.PERIPHERAL,
from_slave_index = 0,
to_slave_type = SlaveType.PERIPHERAL,
to_slave_index = 0):
"""Move slave from one place to another, the slave can be moved from one
bus to another and the index position can be moved."""
if to_slave_type == SlaveType.PERIPHERAL and to_slave_index == 0:
return
if slave_name is None:
gm.SlaveError("a slave name must be specified")
if from_slave_type == to_slave_type:
# Simple move call.
self.sgm.move_slave(from_slave_index, to_slave_index, from_slave_type)
return
sname = self.sgm.get_slave_name_at(from_slave_index, from_slave_type)
node = self.sgm.get_node(sname)
tags = self.sgm.get_parameters(sname)
# moving to the other bus, need to sever connections.
self.remove_slave(from_slave_type, from_slave_index)
filename = saputils.find_module_filename(tags["module"])
filename = saputils.find_rtl_file_location(filename)
self.add_slave(slave_name, filename, to_slave_type, to_slave_index)
def move_slave(self,
slave_name=None,
from_slave_type=SlaveType.PERIPHERAL,
from_slave_index=0,
to_slave_type=SlaveType.PERIPHERAL,
to_slave_index=0):
"""Move slave from one place to another, the slave can be moved from one
bus to another and the index position can be moved."""
if to_slave_type == SlaveType.PERIPHERAL and to_slave_index == 0:
return
if slave_name is None:
gm.SlaveError("a slave name must be specified")
if from_slave_type == to_slave_type:
# Simple move call.
self.sgm.move_slave(from_slave_index, to_slave_index,
from_slave_type)
return
sname = self.sgm.get_slave_name_at(from_slave_index, from_slave_type)
node = self.sgm.get_node(sname)
tags = self.sgm.get_parameters(sname)
# moving to the other bus, need to sever connections.
self.remove_slave(from_slave_type, from_slave_index)
filename = saputils.find_module_filename(tags["module"])
filename = saputils.find_rtl_file_location(filename)
self.add_slave(slave_name, filename, to_slave_type, to_slave_index)
def test_generate_buffer_ftdi_io_handler(self):
absfilepath = saputils.find_rtl_file_location("ft_host_interface.v")
slave_keywords = [
"DRT_ID",
"DRT_FLAGS",
"DRT_SIZE"
]
mtags = saputils.get_module_tags(filename = absfilepath, bus="wishbone", keywords = slave_keywords)
self.gen.wires = [
"clk",
"rst"
]
tags = {}
try:
filename = os.getenv("SAPLIB_BASE") + "/example_project/syc1_proto_gpio_mem.json"
filein = open(filename)
filestr = filein.read()
tags = json.loads(filestr)
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
self.gen.tags = tags
self.gen.bindings = self.gen.tags["bind"]
#self.gen.bindings = self.gen.tags["CONSTRAINTS"]["bind"]
result = self.gen.generate_buffer(name = "uio", module_tags = mtags, io_module = True, debug=self.dbg)
buf = result
# print "out:\n" + buf
self.assertEqual(len(buf) > 0, True)
def gen_script(self, tags = {}, buf = "", debug = True):
out_buf = ""
#Get the DRT version from the DRT info
version = 0x0001
version_string = "{0:0=4X}"
version_string = version_string.format(version)
id = 0x1EAF
id_string = "{0:0=4X}"
id_string = id_string.format(id)
#add 1 for the DRT
number_of_devices = len(tags["SLAVES"])
num_dev_string = "{0:0=8X}"
num_dev_string = num_dev_string.format(number_of_devices)
out_buf = version_string + id_string + "\n"
out_buf = out_buf + num_dev_string + "\n"
out_buf = out_buf + "00000000" + "\n"
out_buf = out_buf + "00000000" + "\n"
if debug:
print "Number of slaves: " + str(len(tags["SLAVES"]))
for i in range (0, len(tags["SLAVES"])):
name = tags["SLAVES"][i]
absfilename = saputils.find_rtl_file_location(name)
slave_keywords = [
"DRT_ID",
"DRT_FLAGS",
"DRT_SIZE"
]
if debug:
print "filename: " + absfilename
local_debug = debug
slave_tags = saputils.get_module_tags(filename = absfilename, bus = "wishbone", keywords = slave_keywords, debug=local_debug)
drt_id_buffer = "{0:0=8X}"
drt_flags_buffer = "{0:0=8X}"
drt_offset_buffer = "{0:0=8X}"
drt_size_buffer = "{0:0=8X}"
offset = 0x01000000 * (i + 1)
for item in slave_tags["keywords"].keys():
if debug:
print "keywords" + item + ":" + slave_tags["keywords"][item]
drt_id_buffer = drt_id_buffer.format(atoi(slave_tags["keywords"]["DRT_ID"]))
drt_flags_buffer = drt_flags_buffer.format(atoi(slave_tags["keywords"]["DRT_FLAGS"]))
drt_offset_buffer = drt_offset_buffer.format(offset)
drt_size_buffer = drt_size_buffer.format(atoi(slave_tags["keywords"]["DRT_SIZE"]))
out_buf = out_buf + drt_id_buffer + "\n"
out_buf = out_buf + drt_flags_buffer + "\n"
out_buf = out_buf + drt_offset_buffer + "\n"
out_buf = out_buf + drt_size_buffer + "\n"
return out_buf
def test_get_number_of_arbitrator_hosts(self):
#the first test should fail
file_name = "wb_gpio.v"
file_name = saputils.find_rtl_file_location(file_name)
m_tags = saputils.get_module_tags(file_name, "wishbone")
result = saparbitrator.get_number_of_arbitrator_hosts(m_tags,
debug=self.dbg)
self.assertEqual(len(result), 0)
#the second test should pass
file_name = "wb_console.v"
file_name = saputils.find_rtl_file_location(file_name)
m_tags = saputils.get_module_tags(file_name, "wishbone")
result = saparbitrator.get_number_of_arbitrator_hosts(m_tags,
debug=self.dbg)
self.assertEqual(len(result), 2)
def is_module_in_file(self, filename, module_name, debug = False):
"""check the file for the module"""
fbuf = ""
#the name is a verilog file, try and open is
try:
filein = open(filename)
fbuf = filein.read()
filein.close()
except IOError as err:
if debug:
print "the file is not a full path... searching RTL"
#didn't find with full path, search for it
try:
filepath = saputils.find_rtl_file_location(filename)
filein = open(filepath)
fbuf = filein.read()
filein.close()
except IOError as err_int:
if debug:
print "couldn't find file in the RTL directory"
return False
if debug:
print "opened file: " + filename
fbuf = saputils.remove_comments(fbuf)
done = False
module_string = fbuf.partition("module")[2]
while (not done):
# if debug:
module_string = module_string.partition("(")[0]
module_string = module_string.strip("#")
module_string = module_string.strip()
if debug:
print "searching through: " + module_string
# module_string = module_string.strip()
# module_string = module_string.partition(" ")[0]
if (len(module_string) == 0):
done = True
if (module_string.endswith("(")):
module_string = module_string.strip("(")
if debug:
print "looking at: " + module_string
if (module_string == module_name):
if debug:
print "found " + module_string + " in " + filename
return True
elif(len(module_string.partition("module")[2]) > 0):
if debug:
print "found another module in the file"
module_string = module_string.partition("module")[2]
else:
done = True
return False
def test_read_user_parameters(self):
filename = saputils.find_rtl_file_location("wb_gpio.v")
tags = saputils.get_module_tags(filename, debug=self.dbg)
keys = tags["parameters"].keys()
if self.dbg:
print "reading the parameters specified by the user"
self.assertIn("DEFAULT_INTERRUPT_MASK", keys)
if self.dbg:
print "make sure other parameters don't get read"
self.assertNotIn("ADDR_GPIO", keys)
def test_is_arbitrator_host(self): """ test if the slave is an arbitrator host """ #the first test should fail file_name = "wb_gpio.v" file_name = saputils.find_rtl_file_location(file_name) m_tags = saputils.get_module_tags(file_name, "wishbone") result = saparbitrator.is_arbitrator_host(m_tags, debug = self.dbg) self.assertEqual(result, False) #the second test should pass file_name = "wb_console.v" file_name = saputils.find_rtl_file_location(file_name) m_tags = saputils.get_module_tags(file_name, "wishbone") result = saparbitrator.is_arbitrator_host(m_tags, debug = self.dbg) self.assertEqual(result, True)
def test_is_arbitrator_host(self):
"""
test if the slave is an arbitrator host
"""
#the first test should fail
file_name = "wb_gpio.v"
file_name = saputils.find_rtl_file_location(file_name)
m_tags = saputils.get_module_tags(file_name, "wishbone")
result = saparbitrator.is_arbitrator_host(m_tags, debug=self.dbg)
self.assertEqual(result, False)
#the second test should pass
file_name = "wb_console.v"
file_name = saputils.find_rtl_file_location(file_name)
m_tags = saputils.get_module_tags(file_name, "wishbone")
result = saparbitrator.is_arbitrator_host(m_tags, debug=self.dbg)
self.assertEqual(result, True)
def test_read_user_parameters(self):
filename = saputils.find_rtl_file_location("wb_gpio.v")
tags = saputils.get_module_tags(filename, debug=self.dbg)
keys = tags["parameters"].keys()
if self.dbg:
print "reading the parameters specified by the user"
self.assertIn("DEFAULT_INTERRUPT_MASK", keys)
if self.dbg:
print "make sure other parameters don't get read"
self.assertNotIn("ADDR_GPIO", keys)
def test_rename_slave(self):
file_name = os.getenv("SAPLIB_BASE") + "/example_project/gpio_example.json"
self.sc.load_config_file(file_name)
self.sc.initialize_graph()
filename = saputils.find_rtl_file_location("wb_console.v")
self.sc.rename_slave(SlaveType.PERIPHERAL, 1, "name1")
name = self.sc.get_slave_name(SlaveType.PERIPHERAL, 1)
self.assertEqual(name, "name1")
def test_generate_with_paramters(self):
"""test the capability to set paramters within the top.v file"""
buf = ""
tags = {}
#load the configuration tags from the json file
try:
filename = os.getenv(
"SAPLIB_BASE") + "/example_project/lx9_parameter_example.json"
filein = open(filename)
filestr = filein.read()
tags = json.loads(filestr)
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
#project tags
self.gen.tags = tags
#module tags
slave_keywords = ["DRT_ID", "DRT_FLAGS", "DRT_SIZE"]
#get the name of the first slave from the configuration file
slave_name = tags["SLAVES"].keys()[0]
#get the module tags from the slave
absfilepath = saputils.find_rtl_file_location(
tags["SLAVES"][slave_name]["filename"])
module_tags = saputils.get_module_tags(filename=absfilepath,
bus="wishbone",
keywords=slave_keywords)
#now we have all the data from the
buf = self.gen.generate_parameters(slave_name,
module_tags,
debug=self.dbg)
# print buf
self.assertEqual(len(buf) > 0, True)
result = self.gen.generate_buffer(slave_name,
index=0,
module_tags=module_tags)
if (self.dbg):
print result
#there are parameters, generate a slave
self.assertEqual(len(result) > 0, True)
def test_find_rtl_file_location(self):
"""give a filename that should be in the RTL"""
result = saputils.find_rtl_file_location("wb_gpio.v")
#print "file location: " + result
try:
testfile = open(result)
result = True
testfile.close()
except:
result = False
self.assertEqual(result, True)
def test_rename_slave(self):
file_name = os.getenv(
"SAPLIB_BASE") + "/example_project/gpio_example.json"
self.sc.load_config_file(file_name)
self.sc.initialize_graph()
filename = saputils.find_rtl_file_location("wb_console.v")
self.sc.rename_slave(SlaveType.PERIPHERAL, 1, "name1")
name = self.sc.get_slave_name(SlaveType.PERIPHERAL, 1)
self.assertEqual(name, "name1")
def test_find_rtl_file_location(self):
"""give a filename that should be in the RTL"""
import saputils
result = saputils.find_rtl_file_location("simple_gpio.v")
#print "file location: " + result
try:
testfile = open(result)
result = True
testfile.close()
except:
result = False
self.assertEqual(result, True)
def has_dependencies(self, filename, debug = False):
"""look in a verilog module, and search for anything that requires a depency, return true if found"""
if debug:
print "input file: " + filename
#filename needs to be a verilog file
if (filename.partition(".")[2] != "v"):
if debug:
print "File is not a recognized verilog source"
return False
fbuf = ""
#the name is a verilog file, try and open is
try:
filein = open(filename)
fbuf = filein.read()
filein.close()
except IOError as err:
if debug:
print "the file is not a full path, searching RTL... ",
#didn't find with full path, search for it
try:
filepath = saputils.find_rtl_file_location(filename)
filein = open(filepath)
fbuf = filein.read()
filein.close()
except IOError as err_int:
if debug:
print "couldn't find file in the RTL directory"
return False
#we have an open file!
if debug:
print "found file!"
#strip out everything we can't use
fbuf = saputils.remove_comments(fbuf)
#modules have lines that start with a '.'
str_list = fbuf.splitlines()
for item in str_list:
item = item.strip()
if (item.startswith(".")):
if debug:
print "found a module!"
return True
return False
def test_generate_with_paramters(self):
"""test the capability to set paramters within the top.v file"""
buf = ""
tags = {}
#load the configuration tags from the json file
try:
filename = os.getenv("SAPLIB_BASE") + "/example_project/lx9_parameter_example.json"
filein = open(filename)
filestr = filein.read()
tags = json.loads(filestr)
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
#project tags
self.gen.tags = tags
#module tags
slave_keywords = [
"DRT_ID",
"DRT_FLAGS",
"DRT_SIZE"
]
#get the name of the first slave from the configuration file
slave_name = tags["SLAVES"].keys()[0]
#get the module tags from the slave
absfilepath = saputils.find_rtl_file_location(tags["SLAVES"][slave_name]["filename"])
module_tags = saputils.get_module_tags(filename = absfilepath, bus="wishbone", keywords = slave_keywords)
#now we have all the data from the
buf = self.gen.generate_parameters(slave_name, module_tags, debug = self.dbg)
# print buf
self.assertEqual(len(buf) > 0, True)
result = self.gen.generate_buffer(slave_name, index = 0, module_tags = module_tags)
if (self.dbg):
print result
#there are parameters, generate a slave
self.assertEqual(len(result) > 0, True)
def test_move_slave_between_bus(self):
file_name = os.getenv(
"SAPLIB_BASE") + "/example_project/gpio_example.json"
self.sc.load_config_file(file_name)
self.sc.initialize_graph()
filename = saputils.find_rtl_file_location("wb_console.v")
self.sc.add_slave("test", filename, SlaveType.PERIPHERAL)
name1 = self.sc.get_slave_name(SlaveType.PERIPHERAL, 2)
self.sc.move_slave("test", SlaveType.PERIPHERAL, 2, SlaveType.MEMORY,
0)
name2 = self.sc.get_slave_name(SlaveType.MEMORY, 0)
self.assertEqual(name1, name2)
def test_move_slave_between_bus(self):
file_name = os.getenv("SAPLIB_BASE") + "/example_project/gpio_example.json"
self.sc.load_config_file(file_name)
self.sc.initialize_graph()
filename = saputils.find_rtl_file_location("wb_console.v")
self.sc.add_slave("test", filename, SlaveType.PERIPHERAL)
name1 = self.sc.get_slave_name(SlaveType.PERIPHERAL, 2)
self.sc.move_slave("test",
SlaveType.PERIPHERAL, 2,
SlaveType.MEMORY, 0)
name2 = self.sc.get_slave_name(SlaveType.MEMORY, 0)
self.assertEqual(name1, name2)
def test_generate_buffer_io_handler(self):
absfilepath = saputils.find_rtl_file_location("uart_io_handler.v")
#print "uart_io_handler.v location: " + absfilepath
tags = saputils.get_module_tags(filename = absfilepath, bus="wishbone")
self.gen.wires=[
"clk",
"rst"
]
result = self.gen.generate_buffer(name = "uio", module_tags = tags)
buf = result
#print "out:\n" + buf
self.assertEqual(len(buf) > 0, True)
def test_move_slave_in_memory_bus(self):
file_name = os.getenv(
"SAPLIB_BASE") + "/example_project/gpio_example.json"
self.sc.load_config_file(file_name)
self.sc.initialize_graph()
filename = saputils.find_rtl_file_location("wb_console.v")
self.sc.add_slave("test1", filename, SlaveType.MEMORY)
self.sc.add_slave("test2", filename, SlaveType.MEMORY)
m_count = self.sc.get_number_of_slaves(SlaveType.MEMORY)
name1 = self.sc.get_slave_name(SlaveType.MEMORY, 0)
self.sc.move_slave("test1", SlaveType.MEMORY, 0, SlaveType.MEMORY, 1)
name2 = self.sc.get_slave_name(SlaveType.MEMORY, 1)
self.assertEqual(name1, name2)
def test_move_slave_in_memory_bus(self):
file_name = os.getenv("SAPLIB_BASE") + "/example_project/gpio_example.json"
self.sc.load_config_file(file_name)
self.sc.initialize_graph()
filename = saputils.find_rtl_file_location("wb_console.v")
self.sc.add_slave("test1", filename, SlaveType.MEMORY)
self.sc.add_slave("test2", filename, SlaveType.MEMORY)
m_count = self.sc.get_number_of_slaves(SlaveType.MEMORY)
name1 = self.sc.get_slave_name(SlaveType.MEMORY, 0)
self.sc.move_slave("test1",
SlaveType.MEMORY, 0,
SlaveType.MEMORY, 1)
name2 = self.sc.get_slave_name(SlaveType.MEMORY, 1)
self.assertEqual(name1, name2)
def set_host_interface(self, host_interface_name, debug = False):
"""Sets the host interface type. If host_interface_name is not a valid
module name (or cannot be found for whatever reason), throws a
ModuleNotFound exception."""
hi_name = self.get_unique_name("Host Interface", NodeType.HOST_INTERFACE)
node_names = self.sgm.get_node_names()
if hi_name not in node_names:
self.sgm.add_node("Host Interface", NodeType.HOST_INTERFACE)
# Check if the host interface is valid.
file_name = saputils.find_module_filename(host_interface_name)
file_name = saputils.find_rtl_file_location(file_name)
# If the host interface is valid then get all the tags ...
parameters = saputils.get_module_tags(filename = file_name,
bus = self.get_bus_type())
# ... and set them up.
self.sgm.set_parameters(hi_name, parameters)
return True
def test_generate_define_table(self):
"""generate a define table given a file"""
import sappreproc
import saputils
filename = saputils.find_rtl_file_location("wb_ddr.v")
print "filename: " + filename
filestring = ""
try:
f = open(filename)
print "opened file"
filestring = f.read()
f.close()
except:
print "Failed to open test filename"
self.assertEqual(True, False)
return
result = sappreproc.generate_define_table(filestring, debug = self.dbg)
self.assertEqual(len(result) > 0, True)
def test_resolve_non_wsp_define(self):
"""First test to see if the system will replace a define that isn't separated by whitespaces"""
import sappreproc
import saputils
#first get the filename
filename = saputils.find_rtl_file_location("wb_ddr.v")
filestring = ""
try:
f = open(filename)
filestring = f.read()
f.close()
except:
print "Failed to open test file"
self.assertEqual(True, False)
return
define_dict = sappreproc.generate_define_table(filestring)
#print "number of defines: " + str(len(define_dict.keys()))
result = sappreproc.resolve_defines("`WB_ADR_WIDTH:0", define_dict, debug = self.dbg)
self.assertEqual(len(result) > 0, True)
def test_generate_define_table(self):
"""generate a define table given a file"""
import sappreproc
import saputils
filename = saputils.find_rtl_file_location("wb_ddr.v")
#print "filename: " + filename
filestring = ""
try:
f = open(filename)
# print "opened file"
filestring = f.read()
f.close()
except:
print "Failed to open test filename"
self.assertEqual(True, False)
return
result = sappreproc.generate_define_table(filestring, debug = self.dbg)
self.assertEqual(len(result) > 0, True)
def test_evaluate_range(self):
"""test whether resolve string will get rid of parenthesis"""
import sappreproc
import saputils
filename = saputils.find_rtl_file_location("wb_ddr.v")
filestring = ""
try:
f = open(filename)
filestring = f.read()
f.close()
except:
print "Failed to open test file"
self.assertEqual(True, False)
return
define_dict = sappreproc.generate_define_table(filestring)
result = sappreproc.evaluate_range("val[(48 -12):0]", debug = self.dbg)
print "final result: " + result
self.assertEqual(result == "val[36:0]", True)
def test_resolve_non_wsp_define(self):
"""First test to see if the system will replace a define that isn't separated by whitespaces"""
import sappreproc
import saputils
#first get the filename
filename = saputils.find_rtl_file_location("wb_ddr.v")
filestring = ""
try:
f = open(filename)
filestring = f.read()
f.close()
except:
print "Failed to open test file"
self.assertEqual(True, False)
return
define_dict = sappreproc.generate_define_table(filestring)
#print "number of defines: " + str(len(define_dict.keys()))
result = sappreproc.resolve_defines("`WB_ADR_WIDTH:0", define_dict, debug = self.dbg)
self.assertEqual(len(result) > 0, True)
def test_evaluate_range(self):
"""test whether resolve string will get rid of parenthesis"""
import sappreproc
import saputils
filename = saputils.find_rtl_file_location("wb_ddr.v")
filestring = ""
try:
f = open(filename)
filestring = f.read()
f.close()
except:
print "Failed to open test file"
self.assertEqual(True, False)
return
define_dict = sappreproc.generate_define_table(filestring)
result = sappreproc.evaluate_range("val[(48 -12):0]", debug = self.dbg)
# print "final result: " + result
self.assertEqual(result == "val[36:0]", True)
def set_host_interface(self, host_interface_name, debug=False):
"""Sets the host interface type. If host_interface_name is not a valid
module name (or cannot be found for whatever reason), throws a
ModuleNotFound exception."""
hi_name = self.get_unique_name("Host Interface",
NodeType.HOST_INTERFACE)
node_names = self.sgm.get_node_names()
if hi_name not in node_names:
self.sgm.add_node("Host Interface", NodeType.HOST_INTERFACE)
# Check if the host interface is valid.
file_name = saputils.find_module_filename(host_interface_name)
file_name = saputils.find_rtl_file_location(file_name)
# If the host interface is valid then get all the tags ...
parameters = saputils.get_module_tags(filename=file_name,
bus=self.get_bus_type())
# ... and set them up.
self.sgm.set_parameters(hi_name, parameters)
return True
def test_resolve_multiple_defines(self):
"""second easiest test, this one requires multiple passes of the
replacement string"""
import sappreproc
import saputils
#first get the filename
filename = saputils.find_rtl_file_location("wb_ddr.v")
filestring = ""
try:
f = open(filename)
filestring = f.read()
f.close()
except:
print "Failed to open test file"
self.assertEqual(True, False)
return
define_dict = sappreproc.generate_define_table(filestring)
#print "number of defines: " + str(len(define_dict.keys()))
result = sappreproc.resolve_defines("`WB_ADR_WIDTH:`WB_SEL_WIDTH", define_dict, debug = self.dbg)
self.assertEqual(len(result) > 0, True)
def test_generate_buffer_slave(self):
absfilepath = saputils.find_rtl_file_location("simple_gpio.v")
#print "simple_gpio.v location: " + absfilepath
slave_keywords = [
"DRT_ID",
"DRT_FLAGS",
"DRT_SIZE"
]
tags = saputils.get_module_tags(filename = absfilepath, bus="wishbone", keywords = slave_keywords)
self.gen.wires = [
"clk",
"rst"
]
result = self.gen.generate_buffer(name="wbs", index=0, module_tags = tags)
buf = result
#print "out:\n" + buf
self.assertEqual(len(buf) > 0, True)
def test_resolve_multiple_defines(self):
"""second easiest test, this one requires multiple passes of the
replacement string"""
import sappreproc
import saputils
#first get the filename
filename = saputils.find_rtl_file_location("wb_ddr.v")
filestring = ""
try:
f = open(filename)
filestring = f.read()
f.close()
except:
print "Failed to open test file"
self.assertEqual(True, False)
return
define_dict = sappreproc.generate_define_table(filestring)
#print "number of defines: " + str(len(define_dict.keys()))
result = sappreproc.resolve_defines("`WB_ADR_WIDTH:`WB_SEL_WIDTH", define_dict, debug = self.dbg)
self.assertEqual(len(result) > 0, True)
def test_generate_buffer_io_handler(self):
absfilepath = saputils.find_rtl_file_location("uart_io_handler.v")
#print "uart_io_handler.v location: " + absfilepath
tags = {}
try:
filename = os.getenv(
"SAPLIB_BASE") + "/example_project/mem_example.json"
filein = open(filename)
filestr = filein.read()
tags = json.loads(filestr)
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
try:
filename = os.getenv(
"SAPLIB_BASE") + "/hdl/rtl/wishbone/wishbone_top.v"
filein = open(filename)
top_buffer = filein.read()
filein.close()
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
#print "buf: " + top_buffer
self.gen.tags = tags
tags = saputils.get_module_tags(filename=absfilepath, bus="wishbone")
self.gen.wires = ["clk", "rst"]
result = self.gen.generate_buffer(name="uio",
module_tags=tags,
io_module=True)
buf = result
#print "out:\n" + buf
self.assertEqual(len(buf) > 0, True)
def test_generate_buffer_io_handler(self):
absfilepath = saputils.find_rtl_file_location("uart_io_handler.v")
#print "uart_io_handler.v location: " + absfilepath
tags = {}
try:
filename = os.getenv("SAPLIB_BASE") + "/example_project/mem_example.json"
filein = open(filename)
filestr = filein.read()
tags = json.loads(filestr)
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
try:
filename = os.getenv("SAPLIB_BASE") + "/hdl/rtl/wishbone/wishbone_top.v"
filein = open(filename)
top_buffer = filein.read()
filein.close()
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
#print "buf: " + top_buffer
self.gen.tags = tags
tags = saputils.get_module_tags(filename = absfilepath, bus="wishbone")
self.gen.wires=[
"clk",
"rst"
]
result = self.gen.generate_buffer(name = "uio", module_tags = tags, io_module = True)
buf = result
#print "out:\n" + buf
self.assertEqual(len(buf) > 0, True)
def test_apply_stave_tags_to_project(self):
file_name = os.getenv(
"SAPLIB_BASE") + "/example_project/arb_example.json"
self.sc.load_config_file(file_name)
self.sc.initialize_graph()
# This example only attaches one of the two arbitrators.
# Attach the second arbitrator.
filename = saputils.find_rtl_file_location("tft.v")
slave_name = self.sc.add_slave("tft1", filename, SlaveType.PERIPHERAL)
host_name = self.sc.sgm.get_slave_name_at(SlaveType.PERIPHERAL, 1)
arb_master = "lcd"
self.sc.add_arbitrator_by_name(host_name, arb_master, slave_name)
# Add a binding for the tft screen.
self.sc.set_binding(slave_name, "data_en", "lcd_e")
# Now we have something sigificantly different than what was loaded in.
self.sc.set_project_name("arbitrator_project")
self.sc.apply_slave_tags_to_project()
pt = self.sc.project_tags
# Check to see if the new slave took.
self.assertIn("tft1", pt["SLAVES"].keys())
# Check to see if the arbitrator was set up.
self.assertIn("lcd", pt["SLAVES"]["console"]["BUS"].keys())
# Check to see if the arbitrator is attached to the slave.
self.assertEqual("tft1", pt["SLAVES"]["console"]["BUS"]["lcd"])
# Check to see if the binding was written.
self.assertIn("data_en", pt["SLAVES"]["tft1"]["bind"].keys())
home_dir = saputils.resolve_linux_path("~")
self.sc.save_config_file(home_dir + "/arb_test_out.json")
def test_apply_stave_tags_to_project(self):
file_name = os.getenv("SAPLIB_BASE") + "/example_project/arb_example.json"
self.sc.load_config_file(file_name)
self.sc.initialize_graph()
# This example only attaches one of the two arbitrators.
# Attach the second arbitrator.
filename = saputils.find_rtl_file_location("tft.v")
slave_name = self.sc.add_slave("tft1", filename, SlaveType.PERIPHERAL)
host_name = self.sc.sgm.get_slave_name_at(SlaveType.PERIPHERAL, 1)
arb_master = "lcd"
self.sc.add_arbitrator_by_name(host_name, arb_master, slave_name)
# Add a binding for the tft screen.
self.sc.set_binding(slave_name, "data_en", "lcd_e")
# Now we have something sigificantly different than what was loaded in.
self.sc.set_project_name("arbitrator_project")
self.sc.apply_slave_tags_to_project()
pt = self.sc.project_tags
# Check to see if the new slave took.
self.assertIn("tft1", pt["SLAVES"].keys())
# Check to see if the arbitrator was set up.
self.assertIn("lcd", pt["SLAVES"]["console"]["BUS"].keys())
# Check to see if the arbitrator is attached to the slave.
self.assertEqual("tft1", pt["SLAVES"]["console"]["BUS"]["lcd"])
# Check to see if the binding was written.
self.assertIn("data_en", pt["SLAVES"]["tft1"]["bind"].keys())
home_dir = saputils.resolve_linux_path("~")
self.sc.save_config_file(home_dir + "/arb_test_out.json")
def gen_script (self, tags = {}, buf = "", debug=False):
"""Overridden function"""
mem_list = []
template = Template(buf)
port_buf = ""
port_def_buf = ""
mem_select_buf = ""
assign_buf = ""
data_block_buf = ""
ack_block_buf = ""
int_block_buf = ""
param_buf = ""
#start with 1 to account for DRT
num_mems = 0
if (tags.has_key("MEMORY")):
#got a list of all the slaves to add to make room for
mem_list = tags["MEMORY"]
num_mems = num_mems + len(mem_list)
if num_mems == 0:
return ""
if debug:
for key in tags["MEMORY"]:
print key + ":" + str(tags["MEMORY"][key])
slave_keywords = [
"DRT_ID",
"DRT_FLAGS",
"DRT_SIZE"
]
mem_offset = 0
#generate the parameters
for i in range(0, num_mems):
key = tags["MEMORY"].keys()[i]
absfilename = saputils.find_rtl_file_location(tags["MEMORY"][key]["filename"])
slave_tags = saputils.get_module_tags(filename = absfilename, bus = "wishbone", keywords = slave_keywords)
if debug:
print "slave tags: " + str(slave_tags)
mem_size = slave_tags["keywords"]["DRT_SIZE"].strip()
param_buf = param_buf + "parameter MEM_SEL_" + str(i) + "\t=\t" + str(i) + ";\n"
param_buf = param_buf + "parameter MEM_OFFSET_" + str(i) + "\t=\t" + str(mem_offset) + ";\n"
param_buf = param_buf + "parameter MEM_SIZE_" + str(i) + "\t=\t" + mem_size + ";\n"
mem_offset += atoi(mem_size)
#generate the memory select logic
mem_select_buf = "reg [31:0] mem_select;\n"
mem_select_buf += "\n"
mem_select_buf += "always @(rst or m_adr_i or mem_select) begin\n"
mem_select_buf += "\tif (rst) begin\n"
mem_select_buf += "\t\t//nothing selected\n"
mem_select_buf += "\t\tmem_select <= 32'hFFFFFFFF;\n"
mem_select_buf += "\tend\n"
mem_select_buf += "\telse begin\n"
for i in range (num_mems):
if (i == 0):
mem_select_buf += "\t\tif "
else:
mem_select_buf += "\t\telse if "
mem_select_buf += "((m_adr_i >= MEM_OFFSET_" + str(i) + ") && (m_adr_i < (MEM_OFFSET_" + str(i) + " + MEM_SIZE_" + str(i) + "))) begin\n"
mem_select_buf += "\t\t\tmem_select <= MEM_SEL_" + str(i) + ";\n"
mem_select_buf += "\t\tend\n"
mem_select_buf += "\t\telse begin\n"
mem_select_buf += "\t\t\tmem_select <= 32'hFFFFFFFF;\n"
mem_select_buf += "\t\tend\n"
mem_select_buf += "\tend\n"
mem_select_buf += "end\n"
#for i in range ( 0, num_mems):
# print "count: " + str(i)
# ports
for i in range (0, num_mems):
port_buf = port_buf + "\ts" + str(i) + "_we_o,\n"
port_buf = port_buf + "\ts" + str(i) + "_cyc_o,\n"
port_buf = port_buf + "\ts" + str(i) + "_stb_o,\n"
port_buf = port_buf + "\ts" + str(i) + "_sel_o,\n"
port_buf = port_buf + "\ts" + str(i) + "_ack_i,\n"
port_buf = port_buf + "\ts" + str(i) + "_dat_o,\n"
port_buf = port_buf + "\ts" + str(i) + "_dat_i,\n"
port_buf = port_buf + "\ts" + str(i) + "_adr_o,\n"
port_buf = port_buf + "\ts" + str(i) + "_int_i"
if ((num_mems > 0) and (i < num_mems - 1)):
port_buf = port_buf + ",\n"
port_buf = port_buf + "\n\n"
# port defines
for i in range (0, num_mems):
port_def_buf = port_def_buf + "output\t\t\ts" + str(i) + "_we_o;\n"
port_def_buf = port_def_buf + "output\t\t\ts" + str(i) + "_cyc_o;\n"
port_def_buf = port_def_buf + "output\t\t\ts" + str(i) + "_stb_o;\n"
port_def_buf = port_def_buf + "output\t[3:0]\t\ts" + str(i) + "_sel_o;\n"
port_def_buf = port_def_buf + "output\t[31:0]\t\ts" + str(i) + "_adr_o;\n"
port_def_buf = port_def_buf + "output\t[31:0]\t\ts" + str(i) + "_dat_o;\n"
port_def_buf = port_def_buf + "input\t[31:0]\t\ts" + str(i) + "_dat_i;\n"
port_def_buf = port_def_buf + "input\t\t\ts" + str(i) + "_ack_i;\n"
port_def_buf = port_def_buf + "input\t\t\ts" + str(i) + "_int_i;\n"
port_def_buf = port_def_buf + "\n\n"
#assign defines
for i in range (0, num_mems):
assign_buf = assign_buf + "assign s" + str(i) + "_we_o\t=\t(mem_select == MEM_SEL_" + str(i) + ") ? m_we_i: 0;\n"
assign_buf = assign_buf + "assign s" + str(i) + "_stb_o\t=\t(mem_select == MEM_SEL_" + str(i) + ") ? m_stb_i: 0;\n"
assign_buf = assign_buf + "assign s" + str(i) + "_sel_o\t=\t(mem_select == MEM_SEL_" + str(i) + ") ? m_sel_i: 0;\n"
assign_buf = assign_buf + "assign s" + str(i) + "_cyc_o\t=\t(mem_select == MEM_SEL_" + str(i) + ") ? m_cyc_i: 0;\n"
assign_buf = assign_buf + "assign s" + str(i) + "_adr_o\t=\t(mem_select == MEM_SEL_" + str(i) + ") ? m_adr_i: 0;\n"
assign_buf = assign_buf + "assign s" + str(i) + "_dat_o\t=\t(mem_select == MEM_SEL_" + str(i) + ") ? m_dat_i: 0;\n"
assign_buf = assign_buf + "\n"
#data in block
data_block_buf = "//data in from slave\n"
data_block_buf = data_block_buf + "always @ (mem_select"
for i in range (0, num_mems):
data_block_buf = data_block_buf + " or s" + str(i) + "_dat_i"
data_block_buf = data_block_buf + ") begin\n\tcase (mem_select)\n"
for i in range (0, num_mems):
data_block_buf = data_block_buf + "\t\tMEM_SEL_" + str(i) + ": begin\n\t\t\tm_dat_o <= s" + str(i) + "_dat_i;\n\t\tend\n";
data_block_buf = data_block_buf + "\t\tdefault: begin\n\t\t\tm_dat_o <= 32\'h0000;\n\t\tend\n\tendcase\nend\n\n"
#ack in block
ack_block_buf = "//ack in from slave\n\n"
ack_block_buf = ack_block_buf + "always @ (mem_select"
for i in range (0, num_mems):
ack_block_buf = ack_block_buf + " or s" + str(i) + "_ack_i"
ack_block_buf = ack_block_buf + ") begin\n\tcase (mem_select)\n"
for i in range (0, num_mems):
ack_block_buf = ack_block_buf + "\t\tMEM_SEL_" + str(i) + ": begin\n\t\t\tm_ack_o <= s" + str(i) + "_ack_i;\n\t\tend\n";
ack_block_buf = ack_block_buf + "\t\tdefault: begin\n\t\t\tm_ack_o <= 1\'h0;\n\t\tend\n\tendcase\nend\n\n"
#int in block
int_block_buf = "//int in from slave\n\n"
int_block_buf = int_block_buf + "always @ (mem_select"
for i in range (0, num_mems):
int_block_buf = int_block_buf + " or s" + str(i) + "_int_i"
int_block_buf = int_block_buf + ") begin\n\tcase (mem_select)\n"
for i in range (0, num_mems):
int_block_buf = int_block_buf + "\t\tMEM_SEL_" + str(i) + ": begin\n\t\t\tm_int_o <= s" + str(i) + "_int_i;\n\t\tend\n";
int_block_buf = int_block_buf + "\t\tdefault: begin\n\t\t\tm_int_o <= 1\'h0;\n\t\tend\n\tendcase\nend\n\n"
if debug:
print "buf: " + buf
buf = template.substitute( PORTS=port_buf,
PORT_DEFINES=port_def_buf,
MEM_SELECT=mem_select_buf,
ASSIGN=assign_buf,
DATA=data_block_buf,
ACK=ack_block_buf,
INT=int_block_buf,
MEM_PARAMS=param_buf)
if debug:
print "buf: " + buf
return buf
def get_name (self):
print "wishbone_mem_interconnect.py"
def gen_script (self, tags = {}, buf = "", debug = False):
"""Generate the Top Module"""
board_dict = saputils.get_board_config(tags["board"])
invert_reset = board_dict["invert_reset"]
en_mem_bus = False
slave_list = tags["SLAVES"]
self.internal_bindings = {}
self.bindings = {}
if "MEMORY" in tags:
# if debug:
# print "Found a memory bus"
if (len(tags["MEMORY"]) > 0):
if debug:
print "found " + str(len(tags["MEMORY"])) + " memory devices"
en_mem_bus = True
num_slaves = len(slave_list) + 1
self.tags = tags
#add the internal bindings
self.internal_bindings = {}
if "internal_bind" in self.tags.keys():
self.internal_bindings = self.tags["internal_bind"]
#print "Internal bindings: %s" % str(self.internal_bindings)
#add the global tags
self.bindings = self.tags["bind"]
#add the interface bindings directly
if "bind" in self.tags["INTERFACE"]:
for if_name in self.tags["INTERFACE"]["bind"]:
self.bindings[if_name] = self.tags["INTERFACE"]["bind"][if_name]
#add each of the slave items to the binding
#insert the names
for slave_name in self.tags["SLAVES"]:
if "bind" in self.tags["SLAVES"][slave_name]:
for bind_name in self.tags["SLAVES"][slave_name]["bind"]:
self.bindings[slave_name + "_" + bind_name] = self.tags["SLAVES"][slave_name]["bind"][bind_name]
if "MEMORY" in self.tags:
#add the slave bindings to the list
for mem_name in self.tags["MEMORY"]:
if "bind" in self.tags["MEMORY"][mem_name]:
for bind_name in self.tags["MEMORY"][mem_name]["bind"]:
self.bindings[mem_name + "_" + bind_name] = self.tags["MEMORY"][mem_name]["bind"][bind_name]
if debug:
print "found " + str(len(slave_list)) + " slaves"
for slave in slave_list:
print slave
#remove all the ports from the possible wires
self.add_ports_to_wires()
template = Template(buf)
header = ""
port_buf = self.generate_ports()
arb_buf = self.generate_arbitrator_buffer()
wr_buf = ""
wi_buf = ""
wmi_buf = ""
wm_buf = ""
footer = ""
header = "module top (\n"
#header = header + "\tclk_in,\n"
header = header + "\tclk,\n"
header = header + "\trst,\n"
for c_index in range(0, len(self.bindings.keys())):
name = self.bindings.keys()[c_index]
header = header + "\t" + self.bindings[name]["port"]
if (c_index < len(self.bindings.keys()) - 1):
header = header + ","
header = header + "\n"
header = header + ");"
footer = "endmodule"
#declare the ports
#in the future utilize the constraints to generate the connections
#declare the wires
wr_buf = wr_buf + "\t//input handler signals\n"
#wr_buf = wr_buf + "\tinput\t\tclk_in;\n"
wr_buf = wr_buf + "\tinput\t\t\tclk;\n"
#wr_buf = wr_buf + "\twire\t\tclk;\n"
self.wires.append("clk")
#self.wires.append("clk_in")
wr_buf = wr_buf + "\tinput\t\t\trst;\n"
self.wires.append("rst")
if invert_reset:
#print "found invert reset!"
wr_buf += "\twire\t\t\trst_n;\n"
self.wires.append("rst_n")
wr_buf = wr_buf + "\twire\t[31:0]\tin_command;\n"
self.wires.append("in_command")
wr_buf = wr_buf + "\twire\t[31:0]\tin_address;\n"
self.wires.append("in_address")
wr_buf = wr_buf + "\twire\t[31:0]\tin_data;\n"
self.wires.append("in_data")
wr_buf = wr_buf + "\twire\t[27:0]\tin_data_count;\n"
self.wires.append("in_data_count")
wr_buf = wr_buf + "\twire\t\t\tih_ready;\n\n"
self.wires.append("ih_ready")
wr_buf = wr_buf + "\twire\t\t\tih_reset;\n\n"
self.wires.append("ih_reset")
wr_buf = wr_buf + "\t//output handler signals\n"
wr_buf = wr_buf + "\twire\t[31:0]\tout_status;\n"
self.wires.append("out_status")
wr_buf = wr_buf + "\twire\t[31:0]\tout_address;\n"
self.wires.append("out_address")
wr_buf = wr_buf + "\twire\t[31:0]\tout_data;\n"
self.wires.append("out_data")
wr_buf = wr_buf + "\twire\t[27:0]\tout_data_count;\n"
self.wires.append("out_data_count")
wr_buf = wr_buf + "\twire\t\t\toh_ready;\n"
self.wires.append("oh_ready")
wr_buf = wr_buf + "\twire\t\t\toh_en;\n\n"
self.wires.append("oh_en")
wr_buf = wr_buf + "\t//master signals\n"
wr_buf = wr_buf + "\twire\t\t\tmaster_ready;\n"
self.wires.append("master_ready")
wr_buf = wr_buf + "\twire\t\t\twbm_we_o;\n"
self.wires.append("wbm_we_o")
wr_buf = wr_buf + "\twire\t\t\twbm_cyc_o;\n"
self.wires.append("wbm_cyc_o")
wr_buf = wr_buf + "\twire\t\t\twbm_stb_o;\n"
self.wires.append("wbm_stb_o")
wr_buf = wr_buf + "\twire\t[3:0]\twbm_sel_o;\n"
self.wires.append("wbm_sel_o")
wr_buf = wr_buf + "\twire\t[31:0]\twbm_adr_o;\n"
self.wires.append("wbm_adr_o")
wr_buf = wr_buf + "\twire\t[31:0]\twbm_dat_i;\n"
self.wires.append("wbm_dat_i")
wr_buf = wr_buf + "\twire\t[31:0]\twbm_dat_o;\n"
self.wires.append("wbm_dat_o")
wr_buf = wr_buf + "\twire\t\t\twbm_ack_i;\n"
self.wires.append("wbm_ack_i")
wr_buf = wr_buf + "\twire\t\t\twbm_int_i;\n\n"
self.wires.append("wbm_int_i")
wr_buf = wr_buf + "\twire\t\t\tmem_we_o;\n"
self.wires.append("mem_we_o")
wr_buf = wr_buf + "\twire\t\t\tmem_cyc_o;\n"
self.wires.append("mem_cyc_o")
wr_buf = wr_buf + "\twire\t\t\tmem_stb_o;\n"
self.wires.append("mem_stb_o")
wr_buf = wr_buf + "\twire\t[3:0]\tmem_sel_o;\n"
self.wires.append("mem_sel_o")
wr_buf = wr_buf + "\twire\t[31:0]\tmem_adr_o;\n"
self.wires.append("mem_adr_o")
wr_buf = wr_buf + "\twire\t[31:0]\tmem_dat_i;\n"
self.wires.append("mem_dat_i")
wr_buf = wr_buf + "\twire\t[31:0]\tmem_dat_o;\n"
self.wires.append("mem_dat_o")
wr_buf = wr_buf + "\twire\t\t\tmem_ack_i;\n"
self.wires.append("mem_ack_i")
wr_buf = wr_buf + "\twire\t\t\tmem_int_i;\n"
self.wires.append("mem_int_i")
wr_buf = wr_buf + "\twire\t[31:0]\twbm_debug_out;\n\n"
self.wires.append("wbm_debug_out");
#put the in clock on the global buffer
#wr_buf = wr_buf + "\t//add a global clock buffer to the input clock\n"
#wr_buf = wr_buf + "\tIBUFG clk_ibuf(.I(clk_in), .O(clk));\n\n"
wr_buf = wr_buf + "\t//slave signals\n\n"
for i in range (0, num_slaves):
wr_buf = wr_buf + "\t//slave " + str(i) + "\n"
wr_buf = wr_buf + "\twire\t\t\ts" + str(i) + "_wbs_we_i;\n"
self.wires.append("s" + str(i) + "_wbs_we_i")
wr_buf = wr_buf + "\twire\t\t\ts" + str(i) + "_wbs_cyc_i;\n"
self.wires.append("s" + str(i) + "_wbs_cyc_i")
wr_buf = wr_buf + "\twire\t[31:0]\ts" + str(i) + "_wbs_dat_i;\n"
self.wires.append("s" + str(i) + "_wbs_dat_i")
wr_buf = wr_buf + "\twire\t[31:0]\ts" + str(i) + "_wbs_dat_o;\n"
self.wires.append("s" + str(i) + "_wbs_dat_o")
wr_buf = wr_buf + "\twire\t[31:0]\ts" + str(i) + "_wbs_adr_i;\n"
self.wires.append("s" + str(i) + "_wbs_adr_i")
wr_buf = wr_buf + "\twire\t\t\ts" + str(i) + "_wbs_stb_i;\n"
self.wires.append("s" + str(i) + "_wbs_stb_i")
wr_buf = wr_buf + "\twire\t[3:0]\ts" + str(i) + "_wbs_sel_i;\n"
self.wires.append("s" + str(i) + "_wbs_sel_i")
wr_buf = wr_buf + "\twire\t\t\ts" + str(i) + "_wbs_ack_o;\n"
self.wires.append("s" + str(i) + "_wbs_ack_o")
wr_buf = wr_buf + "\twire\t\t\ts" + str(i) + "_wbs_int_o;\n\n"
self.wires.append("s" + str(i) + "_wbs_int_o")
if (en_mem_bus):
for i in range (0, len(tags["MEMORY"])):
wr_buf = wr_buf + "\t//mem slave " + str(i) + "\n"
wr_buf = wr_buf + "\twire\t\t\tsm" + str(i) + "_wbs_we_i;\n"
self.wires.append("sm" + str(i) + "_wbs_we_i")
wr_buf = wr_buf + "\twire\t\t\tsm" + str(i) + "_wbs_cyc_i;\n"
self.wires.append("sm" + str(i) + "_wbs_cyc_i")
wr_buf = wr_buf + "\twire\t[31:0]\tsm" + str(i) + "_wbs_dat_i;\n"
self.wires.append("sm" + str(i) + "_wbs_dat_i")
wr_buf = wr_buf + "\twire\t[31:0]\tsm" + str(i) + "_wbs_dat_o;\n"
self.wires.append("sm" + str(i) + "_wbs_dat_o")
wr_buf = wr_buf + "\twire\t[31:0]\tsm" + str(i) + "_wbs_adr_i;\n"
self.wires.append("sm" + str(i) + "_wbs_adr_i")
wr_buf = wr_buf + "\twire\t\t\tsm" + str(i) + "_wbs_stb_i;\n"
self.wires.append("sm" + str(i) + "_wbs_stb_i")
wr_buf = wr_buf + "\twire\t[3:0]\tsm" + str(i) + "_wbs_sel_i;\n"
self.wires.append("sm" + str(i) + "_wbs_sel_i")
wr_buf = wr_buf + "\twire\t\t\tsm" + str(i) + "_wbs_ack_o;\n"
self.wires.append("sm" + str(i) + "_wbs_ack_o")
wr_buf = wr_buf + "\twire\t\t\tsm" + str(i) + "_wbs_int_o;\n\n"
self.wires.append("sm" + str(i) + "_wbs_int_o")
if debug:
print "wr_buf: \n" + wr_buf
#generate the IO handler
io_filename = tags["INTERFACE"]["filename"]
absfilepath = saputils.find_rtl_file_location(io_filename)
io_tags = saputils.get_module_tags(filename = absfilepath, bus = "wishbone")
io_buf = self.generate_buffer(name = "io", module_tags = io_tags, io_module = True)
#for the FPGA
#constraints can be a dictionary with the mappings from device
#to input/output/inout multidimensional values
#this should just be file with text that I can pull in, it will always be
#the same!
#instantiate the connection interface
#should this be another script that is clled within here?
#can I extrapolate the required information directly from the
#file?
#interconnect
wi_buf = "\twishbone_interconnect wi (\n"
wi_buf = wi_buf + "\t\t.clk(clk),\n"
if invert_reset:
wi_buf = wi_buf + "\t\t.rst(rst_n),\n\n"
else:
wi_buf = wi_buf + "\t\t.rst(rst),\n\n"
wi_buf = wi_buf + "\t\t//master\n"
wi_buf = wi_buf + "\t\t.m_we_i(wbm_we_o),\n"
wi_buf = wi_buf + "\t\t.m_cyc_i(wbm_cyc_o),\n"
wi_buf = wi_buf + "\t\t.m_stb_i(wbm_stb_o),\n"
wi_buf = wi_buf + "\t\t.m_sel_i(wbm_sel_o),\n"
wi_buf = wi_buf + "\t\t.m_ack_o(wbm_ack_i),\n"
wi_buf = wi_buf + "\t\t.m_dat_i(wbm_dat_o),\n"
wi_buf = wi_buf + "\t\t.m_dat_o(wbm_dat_i),\n"
wi_buf = wi_buf + "\t\t.m_adr_i(wbm_adr_o),\n"
wi_buf = wi_buf + "\t\t.m_int_o(wbm_int_i),\n\n"
for i in range (0, num_slaves):
wi_buf = wi_buf + "\t\t//slave " + str(i) + "\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_we_o (s" + str(i) + "_wbs_we_i),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_cyc_o(s" + str(i) + "_wbs_cyc_i),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_stb_o(s" + str(i) + "_wbs_stb_i),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_sel_o(s" + str(i) + "_wbs_sel_i),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_ack_i(s" + str(i) + "_wbs_ack_o),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_dat_o(s" + str(i) + "_wbs_dat_i),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_dat_i(s" + str(i) + "_wbs_dat_o),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_adr_o(s" + str(i) + "_wbs_adr_i),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_int_i(s" + str(i) + "_wbs_int_o)"
if (i < num_slaves - 1):
wi_buf = wi_buf + ",\n"
wi_buf = wi_buf + "\n\n"
wi_buf = wi_buf + "\t);"
if debug:
print "wi_buf: \n" + wi_buf
#memory interconnect
if en_mem_bus:
if debug:
print "make the membus"
wmi_buf = "\twishbone_mem_interconnect wmi (\n"
wmi_buf = wmi_buf + "\t\t.clk(clk),\n"
if invert_reset:
wmi_buf = wmi_buf + "\t\t.rst(rst_n),\n\n"
else:
wmi_buf = wmi_buf + "\t\t.rst(rst),\n\n"
wmi_buf = wmi_buf + "\t\t//master\n"
wmi_buf = wmi_buf + "\t\t.m_we_i(mem_we_o),\n"
wmi_buf = wmi_buf + "\t\t.m_cyc_i(mem_cyc_o),\n"
wmi_buf = wmi_buf + "\t\t.m_stb_i(mem_stb_o),\n"
wmi_buf = wmi_buf + "\t\t.m_sel_i(mem_sel_o),\n"
wmi_buf = wmi_buf + "\t\t.m_ack_o(mem_ack_i),\n"
wmi_buf = wmi_buf + "\t\t.m_dat_i(mem_dat_o),\n"
wmi_buf = wmi_buf + "\t\t.m_dat_o(mem_dat_i),\n"
wmi_buf = wmi_buf + "\t\t.m_adr_i(mem_adr_o),\n"
wmi_buf = wmi_buf + "\t\t.m_int_o(mem_int_i),\n\n"
num_mems = len(tags["MEMORY"])
for i in range (0, num_mems):
wmi_buf = wmi_buf + "\t//mem slave " + str(i) + "\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_we_o(sm" + str(i) + "_wbs_we_i),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_cyc_o(sm" + str(i) + "_wbs_cyc_i),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_stb_o(sm" + str(i) + "_wbs_stb_i),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_sel_o(sm" + str(i) + "_wbs_sel_i),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_ack_i(sm" + str(i) + "_wbs_ack_o),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_dat_o(sm" + str(i) + "_wbs_dat_i),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_dat_i(sm" + str(i) + "_wbs_dat_o),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_adr_o(sm" + str(i) + "_wbs_adr_i),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_int_i(sm" + str(i) + "_wbs_int_o)"
if ((num_mems > 0) and (i < num_mems - 1)):
wmi_buf = wmi_buf + ",\n"
wmi_buf = wmi_buf + "\n\n"
wmi_buf = wmi_buf + "\t);"
if debug:
print "wmi_buf: \n" + wmi_buf
#instantiate the io handler
#instantiate the master
wm_buf = wm_buf + "\twishbone_master wm (\n"
wm_buf = wm_buf + "\t\t.clk(clk),\n"
if invert_reset:
wm_buf = wm_buf + "\t\t.rst(rst_n),\n\n"
else:
wm_buf = wm_buf + "\t\t.rst(rst),\n\n"
wm_buf = wm_buf + "\t\t//input handler signals\n"
wm_buf = wm_buf + "\t\t.in_ready(ih_ready),\n"
wm_buf = wm_buf + "\t\t.ih_reset(ih_reset),\n"
wm_buf = wm_buf + "\t\t.in_command(in_command),\n"
wm_buf = wm_buf + "\t\t.in_address(in_address),\n"
wm_buf = wm_buf + "\t\t.in_data(in_data),\n"
wm_buf = wm_buf + "\t\t.in_data_count(in_data_count),\n\n"
wm_buf = wm_buf + "\t\t//output handler signals\n"
wm_buf = wm_buf + "\t\t.out_ready(oh_ready),\n"
wm_buf = wm_buf + "\t\t.out_en(oh_en),\n"
wm_buf = wm_buf + "\t\t.out_status(out_status),\n"
wm_buf = wm_buf + "\t\t.out_address(out_address),\n"
wm_buf = wm_buf + "\t\t.out_data(out_data),\n"
wm_buf = wm_buf + "\t\t.out_data_count(out_data_count),\n"
wm_buf = wm_buf + "\t\t.master_ready(master_ready),\n\n"
wm_buf = wm_buf + "\t\t//interconnect signals\n"
wm_buf = wm_buf + "\t\t.wb_adr_o(wbm_adr_o),\n"
wm_buf = wm_buf + "\t\t.wb_dat_o(wbm_dat_o),\n"
wm_buf = wm_buf + "\t\t.wb_dat_i(wbm_dat_i),\n"
wm_buf = wm_buf + "\t\t.wb_stb_o(wbm_stb_o),\n"
wm_buf = wm_buf + "\t\t.wb_cyc_o(wbm_cyc_o),\n"
wm_buf = wm_buf + "\t\t.wb_we_o(wbm_we_o),\n"
wm_buf = wm_buf + "\t\t.wb_msk_o(wbm_msk_o),\n"
wm_buf = wm_buf + "\t\t.wb_sel_o(wbm_sel_o),\n"
wm_buf = wm_buf + "\t\t.wb_ack_i(wbm_ack_i),\n"
wm_buf = wm_buf + "\t\t.wb_int_i(wbm_int_i),\n\n"
wm_buf = wm_buf + "\t\t//memory interconnect signals\n"
wm_buf = wm_buf + "\t\t.mem_adr_o(mem_adr_o),\n"
wm_buf = wm_buf + "\t\t.mem_dat_o(mem_dat_o),\n"
wm_buf = wm_buf + "\t\t.mem_dat_i(mem_dat_i),\n"
wm_buf = wm_buf + "\t\t.mem_stb_o(mem_stb_o),\n"
wm_buf = wm_buf + "\t\t.mem_cyc_o(mem_cyc_o),\n"
wm_buf = wm_buf + "\t\t.mem_we_o(mem_we_o),\n"
wm_buf = wm_buf + "\t\t.mem_msk_o(mem_msk_o),\n"
wm_buf = wm_buf + "\t\t.mem_sel_o(mem_sel_o),\n"
wm_buf = wm_buf + "\t\t.mem_ack_i(mem_ack_i),\n"
wm_buf = wm_buf + "\t\t.mem_int_i(mem_int_i),\n\n"
wm_buf = wm_buf + "\t\t.debug_out(wbm_debug_out)\n\n";
wm_buf = wm_buf + "\t);"
if debug:
print "wm_buf: \n" + wm_buf
#Arbitrators
#Slaves
slave_index = 0
slave_buffer_list = []
absfilename = saputils.find_rtl_file_location("device_rom_table.v")
slave_tags = saputils.get_module_tags(filename = absfilename, bus="wishbone")
slave_buf = self.generate_buffer(name="drt", index=0, module_tags = slave_tags)
slave_buffer_list.append(slave_buf)
for i in range (0, len(tags["SLAVES"])):
slave_name = tags["SLAVES"].keys()[i]
slave = tags["SLAVES"][slave_name]["filename"]
if debug:
print "Slave name: " + slave
absfilename = saputils.find_rtl_file_location(slave)
slave_tags = saputils.get_module_tags(filename = absfilename, bus="wishbone")
slave_buf = self.generate_buffer(name = slave_name, index = i + 1, module_tags = slave_tags)
slave_buffer_list.append(slave_buf)
#Memory devices
mem_buf = ""
mem_buffer_list = []
if en_mem_bus:
#need to make all the memory devices for the memory bus
mem_index = 0
mem_buffer_list = []
for i in range (0, len(tags["MEMORY"])):
mem_name = tags["MEMORY"].keys()[i]
filename = tags["MEMORY"][mem_name]["filename"]
if debug:
print "Mem device: " + mem_name + ", mem file: " + filename
absfilename = saputils.find_rtl_file_location(filename)
mem_tags = saputils.get_module_tags(filename = absfilename, bus="wishbone")
mem_buf = self.generate_buffer(name = mem_name, index = i, module_tags = mem_tags, mem_slave = True)
mem_buffer_list.append(mem_buf)
buf_bind = ""
buf_bind += "\t//assigns\n"
#Generate the internal bindings
if (len(self.internal_bindings.keys()) > 0):
buf_bind += "\t//Internal Bindings\n"
for key in self.internal_bindings.keys():
buf_bind += "\tassign\t%s\t=\t%s;\n" % (key, self.internal_bindings[key]["signal"])
#Generate the external bindings
if (len(self.bindings.keys()) > 0):
buf_bind += "\t//Bindings to Ports\n"
for key in self.bindings.keys():
if (self.bindings[key]["direction"] == "input"):
buf_bind = buf_bind + "\tassign\t" + key + "\t=\t" + self.bindings[key]["port"] + ";\n"
elif (self.bindings[key]["direction"] == "output"):
buf_bind = buf_bind + "\tassign\t" + self.bindings[key]["port"] + "\t=\t" + key + ";\n"
if invert_reset:
buf_bind += "\tassign\trst_n\t\t=\t~rst;\n"
top_buffer = header + "\n\n"
top_buffer += port_buf + "\n\n"
top_buffer += wr_buf + "\n\n"
top_buffer += io_buf + "\n\n"
top_buffer += wi_buf + "\n\n"
top_buffer += wmi_buf + "\n\n"
if (len(arb_buf) > 0):
top_buffer += arb_buf + "\n\n"
top_buffer += wm_buf + "\n\n"
for slave_buf in slave_buffer_list:
top_buffer = top_buffer + "\n\n" + slave_buf
for mem_buf in mem_buffer_list:
top_buffer = top_buffer + "\n\n" + mem_buf
top_buffer = top_buffer + "\n\n" + buf_bind + "\n\n" + footer
return top_buffer
def initialize_graph(self, debug=False):
"""Initializes the graph and project tags."""
# Clear any previous data.
self.sgm.clear_graph()
# Set the bus type.
if self.project_tags["TEMPLATE"] == "wishbone_template.json":
self.set_bus_type("wishbone")
elif self.project_tags["TEMPLATE"] == "axie_template.json":
self.set_bus_type("axie")
# Add the nodes that are always present.
self.sgm.add_node("Host Interface", NodeType.HOST_INTERFACE)
self.sgm.add_node("Master", NodeType.MASTER)
self.sgm.add_node("Memory", NodeType.MEMORY_INTERCONNECT)
self.sgm.add_node("Peripherals", NodeType.PERIPHERAL_INTERCONNECT)
self.add_slave("DRT", None, SlaveType.PERIPHERAL, slave_index=0)
# Get all the unique names for accessing nodes.
hi_name = self.get_unique_name("Host Interface",
NodeType.HOST_INTERFACE)
m_name = self.get_unique_name("Master", NodeType.MASTER)
mi_name = self.get_unique_name("Memory", NodeType.MEMORY_INTERCONNECT)
pi_name = self.get_unique_name("Peripherals",
NodeType.PERIPHERAL_INTERCONNECT)
drt_name = self.get_unique_name("DRT",
NodeType.SLAVE,
SlaveType.PERIPHERAL,
slave_index=0)
# Attach all the appropriate nodes.
self.sgm.connect_nodes(hi_name, m_name)
self.sgm.connect_nodes(m_name, mi_name)
self.sgm.connect_nodes(m_name, pi_name)
self.sgm.connect_nodes(pi_name, drt_name)
# Get module data for the DRT.
try:
file_name = saputils.find_rtl_file_location("device_rom_table.v")
except ModuleNotFound as ex:
if debug:
print "Invalid Module Name: %s" % (host_interface_name)
parameters = saputils.get_module_tags(filename=file_name,
bus=self.get_bus_type())
self.sgm.set_parameters(drt_name, parameters)
# Attempt to load data from the tags.
sp_count = self.sgm.get_number_of_peripheral_slaves()
if debug:
print "loading %d peripheral slaves" % sp_count
if "SLAVES" in self.project_tags:
for slave_name in self.project_tags["SLAVES"].keys():
file_name = self.project_tags["SLAVES"][slave_name]["filename"]
if "device_rom_table" in file_name:
file_name = None
if file_name is not None:
file_name = saputils.find_rtl_file_location(file_name)
uname = self.add_slave(slave_name, file_name,
SlaveType.PERIPHERAL)
# Add the bindings from the config file.
skeys = self.project_tags["SLAVES"][slave_name].keys()
# print "adding bindings"
# if "bind" not in skeys:
# self.project_tags["SLAVES"][slave_name]["bind"] = {}
if "bind" in skeys:
# print "found binding"
bindings = {}
bindings = self.project_tags["SLAVES"][slave_name]["bind"]
self.sgm.set_config_bindings(uname, bindings)
else:
self.project_tags["SLAVES"][slave_name]["bind"] = {}
# Load all the memory slaves.
sm_count = self.sgm.get_number_of_memory_slaves()
if debug:
print "loading %d peripheral slaves" % sm_count
if "MEMORY" in self.project_tags:
for slave_name in self.project_tags["MEMORY"].keys():
file_name = self.project_tags["MEMORY"][slave_name]["filename"]
file_name = saputils.find_rtl_file_location(file_name)
uname = self.add_slave(slave_name,
file_name,
SlaveType.MEMORY,
slave_index=-1)
# Add the bindings from the config file.
mkeys = self.project_tags["MEMORY"][slave_name].keys()
if "bind" in mkeys:
bindings = self.project_tags["MEMORY"][slave_name]["bind"]
self.sgm.set_config_bindings(uname, bindings)
else:
self.project_tags["MEMORY"][slave_name]["bind"] = {}
# Check if there is a host interface defined.
if "INTERFACE" in self.project_tags:
file_name = saputils.find_rtl_file_location(
self.project_tags["INTERFACE"]["filename"])
parameters = saputils.get_module_tags(filename=file_name,
bus=self.get_bus_type())
self.set_host_interface(parameters["module"])
if "bind" in self.project_tags["INTERFACE"].keys():
self.sgm.set_config_bindings(
hi_name, self.project_tags["INTERFACE"]["bind"])
else:
self.project_tags["INTERFACE"]["bind"] = {}
self.sgm.set_parameters(hi_name, parameters)
if "SLAVES" in self.project_tags:
for host_name in self.project_tags["SLAVES"].keys():
if "BUS" in self.project_tags["SLAVES"][host_name].keys():
for arb_name in self.project_tags["SLAVES"][host_name][
"BUS"].keys():
#there is an arbitrator here
slave_name = self.project_tags["SLAVES"][host_name][
"BUS"][arb_name]
if debug:
print "arbitrator: %s attaches to %s through bus: %s" % (
host_name, slave_name, arb_name)
h_name = ""
h_index = -1
h_type = SlaveType.PERIPHERAL
s_name = ""
s_index = -1
s_type = SlaveType.PERIPHERAL
# Now to attach the arbitrator.
p_count = self.get_number_of_slaves(
SlaveType.PERIPHERAL)
m_count = self.get_number_of_slaves(SlaveType.MEMORY)
# Find the host and slave nodes.
for i in range(0, p_count):
self.sgm.get_slave_name_at(i, SlaveType.PERIPHERAL)
sn = self.sgm.get_slave_name_at(
i, SlaveType.PERIPHERAL)
slave = self.sgm.get_node(sn)
if slave.name == host_name:
h_name = slave.unique_name
h_index = i
h_type = SlaveType.PERIPHERAL
if slave.name == slave_name:
s_name = slave.unique_name
s_index = i
s_type = SlaveType.PERIPHERAL
for i in range(0, m_count):
self.sgm.get_slave_name_at(i, SlaveType.MEMORY)
sn = self.sgm.get_slave_name_at(
i, SlaveType.MEMORY)
slave = self.sgm.get_node(sn)
if slave.name == host_name:
h_name = slave.unique_name
h_index = i
h_type = SlaveType.MEMORY
if slave.name == slave_name:
s_name = slave.unique_name
s_index = i
s_type = SlaveType.MEMORY
# Now I have all the materialst to attach the arbitrator.
self.add_arbitrator(h_type, h_index, arb_name, s_type,
s_index)
return True
def generate_define_table(filestring="", debug=False):
"""Reads in a module as a buffer and returns a dictionary of defines
Generates a table of defines that can be used to resolve values.
If all the defines cannot be evaluated directly by the
current module then this will search all the included modules
Args:
filestring: A buffer from the module's file
Returns:
A dictionary of defines
Raises:
PreProcessorError
"""
import saputils
define_dict = {}
#from a file string find all the defines and generate an entry into a dictionary
filestring = saputils.remove_comments(filestring)
str_list = filestring.splitlines()
for item in str_list:
item = item.strip()
#look for include files
if item.startswith("`include"):
if debug:
print "found an include: " + item
#read int the include file, strip away the comments
#then append everything to the end
item = item.partition("`include")[2]
item = item.strip()
item = item.strip("\"")
inc_file = saputils.find_rtl_file_location(item)
if debug:
print "include file location: " + inc_file
#try and open the include file
try:
ifile = open(inc_file)
fs = ifile.read()
ifile.close()
except:
if item != "project_defines.v":
raise PreProcessor(
"Error while attempting to the include file: %s" %
inc_file)
try:
if debug:
print "got the new file string"
include_defines = generate_define_table(fs)
if debug:
print "after include_define"
print "length of include defines: " + str(
len(include_defines.keys()))
for key in include_defines.keys():
#append the values found in the include back in the local dictionary
if debug:
print "working on: " + key
if (not define_dict.has_key(key)):
define_dict[key] = include_defines[key]
if debug:
print "added new items onto the list"
# except TypeError as terr:
# print "Type Error: " + str(terr)
except:
if item != "project_defines.v":
raise PreProcessorError("Error while processing: %s: %s" %
(item, sys.exc_info()[0]))
#print "error while processing : ", item, ": ", sys.exc_info()[0]
continue
if item.startswith("`define"):
#if the string starts with `define split the name and value into the dictionary
# if debug:
# print "found a define: " + item
item = item.partition("`define")[2]
item = item.strip()
if (len(item.partition(" ")[2]) > 0):
name = item.partition(" ")[0].strip()
value = item.partition(" ")[2].strip()
if debug:
print "added " + name + "\n\tWith value: " + value
define_dict[name] = value
continue
if (len(item.partition("\t")[2]) > 0):
name = item.partition("\t")[0].strip()
value = item.partition("\t")[2].strip()
if debug:
print "added " + name + "\n\tWith value: " + value
define_dict[name] = value
continue
if debug:
print "found a define without a value: " + item
return define_dict
def generate_define_table(filestring="", debug = False):
"""Read in a file in string format and create a dictionary relating define name and value"""
import saputils
define_dict = {}
#from a file string find all the defines and generate an entry into a dictionary
filestring = saputils.remove_comments(filestring)
str_list = filestring.splitlines()
for item in str_list:
item = item.strip()
if item.startswith("`include"):
if debug:
print "found an include: " + item
#read int the include file, strip away the comments
#then append everything to the end
item = item.partition("`include")[2]
item = item.strip()
item = item.strip("\"")
inc_file = saputils.find_rtl_file_location(item)
if debug:
print "include file location: " + inc_file
try:
ifile = open(inc_file)
fs = ifile.read()
ifile.close()
if debug:
print "got the new file string"
include_defines = generate_define_table(fs)
if debug:
print "after include_define"
print "length of include defines: " + str(len(include_defines.keys()))
for key in include_defines.keys():
#append the values found in the include back in the local dictionary
if debug:
print "working on: " + key
if (not define_dict.has_key(key)):
define_dict[key] = include_defines[key]
if debug:
print "added new items onto the list"
except TypeError as terr:
print "Type Error: " + str(terr)
except:
print "error while processing : ", item, ": ", sys.exc_info()[0]
continue
if item.startswith("`define"):
#if the string starts with `define split the name and value into the dictionary
# if debug:
# print "found a define: " + item
item = item.partition("`define")[2]
item = item.strip()
if (len(item.partition(" ")[2]) > 0):
name = item.partition(" ")[0].strip()
value = item.partition(" ")[2].strip()
if debug:
print "added " + name + "\n\tWith value: " + value
define_dict[name] = value
continue
if (len(item.partition("\t")[2]) > 0):
name = item.partition("\t")[0].strip()
value = item.partition("\t")[2].strip()
if debug:
print "added " + name + "\n\tWith value: " + value
define_dict[name] = value
continue
if debug:
print "found a define without a value: " + item
return define_dict
def process_file(self,
filename="",
file_dict={},
directory="",
debug=False):
"""process_file
read in a file, modify it (if necessary), then write it to the location
specified by the directory variable
Args:
filename: the name of the file to process
file_dict: dictionary associated with this file
directory: output directory
Return:
Raises:
ModuleFactoryError
IOError
"""
if (len(filename) == 0):
raise ModuleFactoryError("No filename specified")
if (len(directory) == 0):
raise ModuleFactoryError("No output directory specified")
if (filename.endswith(".v")):
self.verilog_file_list.append(filename)
if debug:
print "in process file"
print "\t%s" % filename
#maybe load a tags??
#using the location value in the file_dict find the file and
#pull it into a buf
self.buf = ""
file_location = ""
#There are two types of files
#ones that are copied over from a location
#ones that are generated by scripts
#The file is specified by a location and basically needs to be copied over
if file_dict.has_key("location"):
file_location = os.getenv(
"SAPLIB_BASE") + "/" + file_dict["location"]
if (debug):
print("getting file: " + filename + " from location: " +
file_location)
found_file = False
try:
filein = open(
saputils.resolve_linux_path(file_location + "/" +
filename))
self.buf = filein.read()
filein.close()
found_file = True
except IOError as err:
pass
if not found_file:
if debug:
print "searching for file...",
try:
absfilename = saputils.find_rtl_file_location(filename)
filein = open(absfilename)
self.buf = filein.read()
filein.close()
except:
if debug:
print "Failed to find file"
raise ModuleFactoryError("File %s not found searched %s and in the HDL dir \n \
(%s)" % (filename, \
file_location, \
os.getenv("SAPLIB_BASE") + "/hdl/rtl"))
if debug:
print "found file!"
print "file content: " + self.buf
#File is generated by a script
elif (not file_dict.has_key("gen_script")):
raise ModuleFactoryError(
"File %s does not declare a location or a script! Check the template file"
% filename)
if (debug):
print "Project name: " + self.tags["PROJECT_NAME"]
#if the generation flag is set in the dictionary
if (file_dict.has_key("gen_script")):
if (debug):
print "found the generation script"
print "run generation script: " + file_dict["gen_script"]
#open up the new gen module
cl = __import__("gen")
if debug:
print "cl: " + str(cl)
Gen = getattr(cl, "Gen")
if debug:
print "Gen: " + str(Gen)
self.gen_module = __import__(file_dict["gen_script"])
gen_success_flag = False
#find the script and dynamically add it
for name in dir(self.gen_module):
obj = getattr(self.gen_module, name)
# print "object type: " + str(obj)
#XXX: debug section start
if debug:
print "name: " + name
if isclass(obj):
if debug:
print "\tobject type: " + str(obj)
print "\tis class"
if issubclass(obj, cl.Gen):
if debug:
print "\t\tis subclass"
#XXX: debug section end
if isclass(obj) and issubclass(obj, Gen) and obj is not Gen:
self.gen = obj()
if debug:
print "obj = " + str(self.gen)
self.buf = self.gen.gen_script(tags=self.tags,
buf=self.buf)
gen_success_flag = True
if not gen_success_flag:
raise ModuleFactoryError(
"Failed to execute the generation script %s" %
file_dict["gen_script"])
else:
#no script to execute, just tags
self.apply_tags()
if debug:
print self.buf
#write the file to the specified directory
if (len(self.buf) > 0):
result = self.write_file(directory, filename)
if (self.has_dependencies(filename)):
deps = self.get_list_of_dependencies(filename)
for d in deps:
try:
result = saputils.find_module_filename(d)
if (len(result) == 0):
print "Error: couldn't find dependency filename"
continue
f = saputils.find_module_filename(d)
if (f not in self.verilog_dependency_list
and f not in self.verilog_file_list):
if debug:
print "found dependency: " + f
self.verilog_dependency_list.append(f)
except ModuleNotFound as err:
continue
def initialize_graph(self, debug=False):
"""Initializes the graph and project tags."""
# Clear any previous data.
self.sgm.clear_graph()
# Set the bus type.
if self.project_tags["TEMPLATE"] == "wishbone_template.json":
self.set_bus_type("wishbone")
elif self.project_tags["TEMPLATE"] == "axie_template.json":
self.set_bus_type("axie")
# Add the nodes that are always present.
self.sgm.add_node("Host Interface", NodeType.HOST_INTERFACE)
self.sgm.add_node("Master", NodeType.MASTER)
self.sgm.add_node("Memory", NodeType.MEMORY_INTERCONNECT)
self.sgm.add_node("Peripherals", NodeType.PERIPHERAL_INTERCONNECT)
self.add_slave("DRT", None, SlaveType.PERIPHERAL, slave_index = 0)
# Get all the unique names for accessing nodes.
hi_name = self.get_unique_name("Host Interface", NodeType.HOST_INTERFACE)
m_name = self.get_unique_name("Master", NodeType.MASTER)
mi_name = self.get_unique_name("Memory", NodeType.MEMORY_INTERCONNECT)
pi_name = self.get_unique_name("Peripherals", NodeType.PERIPHERAL_INTERCONNECT)
drt_name = self.get_unique_name("DRT",
NodeType.SLAVE,
SlaveType.PERIPHERAL,
slave_index = 0)
# Attach all the appropriate nodes.
self.sgm.connect_nodes(hi_name, m_name)
self.sgm.connect_nodes(m_name, mi_name)
self.sgm.connect_nodes(m_name, pi_name)
self.sgm.connect_nodes(pi_name, drt_name)
# Get module data for the DRT.
try:
file_name = saputils.find_rtl_file_location("device_rom_table.v")
except ModuleNotFound as ex:
if debug:
print "Invalid Module Name: %s" % (host_interface_name)
parameters = saputils.get_module_tags( filename = file_name, bus=self.get_bus_type())
self.sgm.set_parameters(drt_name, parameters)
# Attempt to load data from the tags.
sp_count = self.sgm.get_number_of_peripheral_slaves()
if debug:
print "loading %d peripheral slaves" % sp_count
if "SLAVES" in self.project_tags:
for slave_name in self.project_tags["SLAVES"].keys():
file_name = self.project_tags["SLAVES"][slave_name]["filename"]
if "device_rom_table" in file_name:
file_name = None
if file_name is not None:
file_name = saputils.find_rtl_file_location(file_name)
uname = self.add_slave( slave_name,
file_name,
SlaveType.PERIPHERAL)
# Add the bindings from the config file.
skeys = self.project_tags["SLAVES"][slave_name].keys()
# print "adding bindings"
# if "bind" not in skeys:
# self.project_tags["SLAVES"][slave_name]["bind"] = {}
if "bind" in skeys:
# print "found binding"
bindings = {}
bindings = self.project_tags["SLAVES"][slave_name]["bind"]
self.sgm.set_config_bindings(uname, bindings)
else:
self.project_tags["SLAVES"][slave_name]["bind"] = {}
# Load all the memory slaves.
sm_count = self.sgm.get_number_of_memory_slaves()
if debug:
print "loading %d peripheral slaves" % sm_count
if "MEMORY" in self.project_tags:
for slave_name in self.project_tags["MEMORY"].keys():
file_name = self.project_tags["MEMORY"][slave_name]["filename"]
file_name = saputils.find_rtl_file_location(file_name)
uname = self.add_slave( slave_name,
file_name,
SlaveType.MEMORY,
slave_index = -1)
# Add the bindings from the config file.
mkeys = self.project_tags["MEMORY"][slave_name].keys()
if "bind" in mkeys:
bindings = self.project_tags["MEMORY"][slave_name]["bind"]
self.sgm.set_config_bindings(uname, bindings)
else:
self.project_tags["MEMORY"][slave_name]["bind"] = {}
# Check if there is a host interface defined.
if "INTERFACE" in self.project_tags:
file_name = saputils.find_rtl_file_location(self.project_tags["INTERFACE"]["filename"])
parameters = saputils.get_module_tags( filename = file_name, bus=self.get_bus_type())
self.set_host_interface(parameters["module"])
if "bind" in self.project_tags["INTERFACE"].keys():
self.sgm.set_config_bindings(hi_name,
self.project_tags["INTERFACE"]["bind"])
else:
self.project_tags["INTERFACE"]["bind"] = {}
self.sgm.set_parameters(hi_name, parameters)
if "SLAVES" in self.project_tags:
for host_name in self.project_tags["SLAVES"].keys():
if "BUS" in self.project_tags["SLAVES"][host_name].keys():
for arb_name in self.project_tags["SLAVES"][host_name]["BUS"].keys():
#there is an arbitrator here
slave_name = self.project_tags["SLAVES"][host_name]["BUS"][arb_name]
if debug:
print "arbitrator: %s attaches to %s through bus: %s" % (host_name, slave_name, arb_name)
h_name = ""
h_index = -1
h_type = SlaveType.PERIPHERAL
s_name = ""
s_index = -1
s_type = SlaveType.PERIPHERAL
# Now to attach the arbitrator.
p_count = self.get_number_of_slaves(SlaveType.PERIPHERAL)
m_count = self.get_number_of_slaves(SlaveType.MEMORY)
# Find the host and slave nodes.
for i in range (0, p_count):
self.sgm.get_slave_name_at(i, SlaveType.PERIPHERAL)
sn = self.sgm.get_slave_name_at(i, SlaveType.PERIPHERAL)
slave = self.sgm.get_node(sn)
if slave.name == host_name:
h_name = slave.unique_name
h_index = i
h_type = SlaveType.PERIPHERAL
if slave.name == slave_name:
s_name = slave.unique_name
s_index = i
s_type = SlaveType.PERIPHERAL
for i in range (0, m_count):
self.sgm.get_slave_name_at(i, SlaveType.MEMORY)
sn = self.sgm.get_slave_name_at(i, SlaveType.MEMORY)
slave = self.sgm.get_node(sn)
if slave.name == host_name:
h_name = slave.unique_name
h_index = i
h_type = SlaveType.MEMORY
if slave.name == slave_name:
s_name = slave.unique_name
s_index = i
s_type = SlaveType.MEMORY
# Now I have all the materialst to attach the arbitrator.
self.add_arbitrator(h_type, h_index, arb_name, s_type, s_index)
return True
def gen_script(self, tags={}, buf="", debug=False):
out_buf = ""
#Get the DRT version from the DRT info
version = 0x0004
version_string = "{0:0=4X}"
version_string = version_string.format(version)
id = 0xC594
id_string = "{0:0=4X}"
id_string = id_string.format(id)
#add 1 for the DRT
number_of_devices = 0
#number_of_devices = 1
number_of_devices += len(tags["SLAVES"])
if debug:
print "number of slaves: " + str(number_of_devices)
if ("MEMORY" in tags):
if debug:
print "num of mem devices: " + str(len(tags["MEMORY"]))
number_of_devices += len(tags["MEMORY"])
if debug:
print "number of entities: " + str(number_of_devices)
num_dev_string = "{0:0=8X}"
num_dev_string = num_dev_string.format(number_of_devices)
#header
out_buf = version_string + id_string + "\n"
out_buf += num_dev_string + "\n"
out_buf += "00000000" + "\n"
out_buf += "00000000" + "\n"
out_buf += "00000000" + "\n"
out_buf += "00000000" + "\n"
out_buf += "00000000" + "\n"
out_buf += "00000000" + "\n"
#peripheral slaves
for i in range(0, len(tags["SLAVES"])):
key = tags["SLAVES"].keys()[i]
name = tags["SLAVES"][key]["filename"]
absfilename = saputils.find_rtl_file_location(name)
slave_keywords = ["DRT_ID", "DRT_FLAGS", "DRT_SIZE"]
slave_tags = saputils.get_module_tags(filename=absfilename,
bus="wishbone",
keywords=slave_keywords)
drt_id_buffer = "{0:0=8X}"
drt_flags_buffer = "{0:0=8X}"
drt_offset_buffer = "{0:0=8X}"
drt_size_buffer = "{0:0=8X}"
offset = 0x01000000 * (i + 1)
drt_id_buffer = drt_id_buffer.format(
atoi(slave_tags["keywords"]["DRT_ID"].strip()))
drt_flags_buffer = drt_flags_buffer.format(
0x00000000 + atoi(slave_tags["keywords"]["DRT_FLAGS"]))
drt_offset_buffer = drt_offset_buffer.format(offset)
drt_size_buffer = drt_size_buffer.format(
atoi(slave_tags["keywords"]["DRT_SIZE"]))
out_buf += drt_id_buffer + "\n"
out_buf += drt_flags_buffer + "\n"
out_buf += drt_offset_buffer + "\n"
out_buf += drt_size_buffer + "\n"
out_buf += "00000000\n"
out_buf += "00000000\n"
out_buf += "00000000\n"
out_buf += "00000000\n"
#memory slaves
if ("MEMORY" in tags):
mem_offset = 0
for i in range(0, len(tags["MEMORY"])):
key = tags["MEMORY"].keys()[i]
name = tags["MEMORY"][key]["filename"]
absfilename = saputils.find_rtl_file_location(name)
slave_keywords = ["DRT_ID", "DRT_FLAGS", "DRT_SIZE"]
slave_tags = saputils.get_module_tags(filename=absfilename,
bus="wishbone",
keywords=slave_keywords)
drt_id_buffer = "{0:0=8X}"
drt_flags_buffer = "{0:0=8X}"
drt_offset_buffer = "{0:0=8X}"
drt_size_buffer = "{0:0=8X}"
#add the offset from the memory
drt_id_buffer = drt_id_buffer.format(
atoi(slave_tags["keywords"]["DRT_ID"]))
drt_flags_buffer = drt_flags_buffer.format(
0x00010000 + atoi(slave_tags["keywords"]["DRT_FLAGS"]))
drt_offset_buffer = drt_offset_buffer.format(mem_offset)
drt_size_buffer = drt_size_buffer.format(
atoi(slave_tags["keywords"]["DRT_SIZE"]))
mem_offset += atoi(slave_tags["keywords"]["DRT_SIZE"])
out_buf += drt_id_buffer + "\n"
out_buf += drt_flags_buffer + "\n"
out_buf += drt_offset_buffer + "\n"
out_buf += drt_size_buffer + "\n"
out_buf += "00000000\n"
out_buf += "00000000\n"
out_buf += "00000000\n"
out_buf += "00000000\n"
return out_buf
def has_dependencies(self, filename, debug=False):
"""has_dependencies
returns true if the file specified has dependencies
Args:
filename: search for dependencies with this filename
Return:
True: The file has dependencies.
False: The file doesn't have dependencies
Raises:
IOError
"""
if debug:
print "input file: " + filename
#filename needs to be a verilog file
if (filename.partition(".")[2] != "v"):
if debug:
print "File is not a recognized verilog source"
return False
fbuf = ""
#the name is a verilog file, try and open is
try:
filein = open(filename)
fbuf = filein.read()
filein.close()
except IOError as err:
if debug:
print "the file is not a full path, searching RTL... ",
#didn't find with full path, search for it
try:
filepath = saputils.find_rtl_file_location(filename)
filein = open(filepath)
fbuf = filein.read()
filein.close()
except IOError as err_int:
if debug:
print "couldn't find file in the RTL directory"
ModuleFactoryError(
"Couldn't find file %s in the RTL directory" % filename)
#we have an open file!
if debug:
print "found file!"
#strip out everything we can't use
fbuf = saputils.remove_comments(fbuf)
#modules have lines that start with a '.'
str_list = fbuf.splitlines()
for item in str_list:
item = item.strip()
if (item.startswith(".")):
if debug:
print "found a module!"
return True
return False
def process_file(self, filename = "", file_dict={}, directory="", debug=False):
"""read in a file, modify it (if necessary), then wite it to the location specified by the director variable"""
if (len(filename) == 0):
return False
if (len(directory) == 0):
return False
if (filename.endswith(".v")):
self.verilog_file_list.append(filename)
if (debug):
print "in process file"
#maybe load a tags??
#using the location value in the file_dict find the file and
#pull it into a buf
self.buf = ""
file_location = ""
if file_dict.has_key("location"):
file_location = os.getenv("SAPLIB_BASE") + "/" + file_dict["location"]
if (debug):
print ("getting file: " + filename + " from location: " + file_location)
result = self.read_file(file_location + "/" + filename)
if (not result):
if debug:
print "searching for file...",
absfilename = saputils.find_rtl_file_location(filename)
result = self.read_file(absfilename)
if result:
if debug:
print "found file!"
else:
if debug:
print "failed to find file"
if (len(self.buf) == 0):
if debug:
print "File wasn't found!"
return False
if debug:
print "file content: " + self.buf
elif (not file_dict.has_key("gen_script")):
if debug:
print "didn't find file location"
return False
if (debug):
print "Project name: " + self.tags["PROJECT_NAME"]
#if the generation flag is set in the dictionary
if (file_dict.has_key("gen_script")):
if (debug):
print "found the generation script"
print "run generation script: " + file_dict["gen_script"]
#open up the new gen module
cl = __import__("gen")
print "cl: " + str(cl)
Gen = getattr(cl, "Gen")
print "Gen: " + str(Gen)
self.gen_module = __import__(file_dict["gen_script"])
gen_success_flag = False
for name in dir(self.gen_module):
obj = getattr(self.gen_module, name)
# print "object type: " + str(obj)
#debug section start
print "name: " + name
if isclass(obj):
print "\tobject type: " + str(obj)
print "\tis class"
if issubclass(obj, cl.Gen):
print "\t\tis subclass"
#debug section end
if isclass(obj) and issubclass(obj, Gen) and obj is not Gen:
self.gen = obj()
print "obj = " + str(self.gen)
self.buf = self.gen.gen_script(tags = self.tags, buf = self.buf)
gen_success_flag = True
if (not gen_success_flag):
print "FAILED TO EXECUTE GENSCRIPT " + file_dict["gen_script"]
else:
#perform the format function
self.apply_tags()
if (debug):
print self.buf
#write the file to the specified directory
result = self.write_file(directory, filename)
if (self.has_dependencies(filename)):
deps = self.get_list_of_dependencies(filename)
for d in deps:
result = self.find_module_filename(d)
if (len(result) == 0):
print "Error couldn't find dependency filename"
continue
f = self.find_module_filename(d)
if (not self.verilog_dependency_list.__contains__(f) and
not self.verilog_file_list.__contains__(f)):
if debug:
print "found dependency: " + f
self.verilog_dependency_list.append(f)
return True
def get_list_of_dependencies(self, filename, debug=False):
"""get_list_of_dependencies
return a list of the files that this file depends on
Args:
filename: the name of the file to analyze
Return:
A list of files that specify the dependenies
Raises:
IOError
"""
deps = []
if debug:
print "input file: " + filename
#filename needs to be a verilog file
if (filename.partition(".")[2] != "v"):
if debug:
print "File is not a recognized verilog source"
return False
fbuf = ""
#the name is a verilog file, try and open is
try:
filein = open(filename)
fbuf = filein.read()
filein.close()
except IOError as err:
#if debug:
# print "the file is not a full path... searching RTL"
#didn't find with full path, search for it
try:
filepath = saputils.find_rtl_file_location(filename)
filein = open(filepath)
fbuf = filein.read()
filein.close()
except IOError as err_int:
ModuleFactoryError(
"Couldn't find file %s in the RTL directory" % filename)
#we have an open file!
if debug:
print "found file!"
#strip out everything we can't use
fbuf = saputils.remove_comments(fbuf)
include_fbuf = fbuf
#search for `include
while (not len(include_fbuf.partition("`include")[2]) == 0):
ifile_name = include_fbuf.partition("`include")[2]
ifile_name = ifile_name.splitlines()[0]
ifile_name = ifile_name.strip()
ifile_name = ifile_name.strip("\"")
if debug:
print "found an include " + ifile_name + " ",
if (not self.verilog_dependency_list.__contains__(ifile_name)
and not self.verilog_file_list.__contains__(ifile_name)):
self.verilog_dependency_list.append(ifile_name)
if debug:
print "adding " + ifile_name + " to the dependency list"
else:
if debug:
print "... already in have it"
include_fbuf = include_fbuf.partition("`include")[2]
#remove the ports list and the module name
fbuf = fbuf.partition(")")[2]
#modules have lines that start with a '.'
str_list = fbuf.splitlines()
module_token = ""
done = False
while (not done):
for i in range(0, len(str_list)):
line = str_list[i]
#remove white spaces
line = line.strip()
if (line.startswith(".") and line.endswith(",")):
#if debug:
# print "found a possible module... with token: " + line
module_token = line
break
#check if we reached the last line
if (i >= len(str_list) - 1):
done = True
if (not done):
#found a possible module
#partitoin the fbuf
#if debug:
# print "module token " + module_token
module_string = fbuf.partition(module_token)[0]
fbuf = fbuf.partition(module_token)[2]
fbuf = fbuf.partition(";")[2]
str_list = fbuf.splitlines()
#get rid of everything before the possible module
while (len(module_string.partition(";")[2]) > 0):
module_string = module_string.partition(";")[2]
module_string = module_string.partition("(")[0]
module_string = module_string.strip("#")
module_string = module_string.strip()
m_name = module_string.partition(" ")[0]
if debug:
print "module name: " + m_name
if (not deps.__contains__(m_name)):
if debug:
print "adding it to the deps list"
deps.append(module_string.partition(" ")[0])
#mlist = module_string.splitlines()
#work backwords
#look for the last line that has a '('
#for i in range (0, len(mlist)):
# mstr = mlist[i]
# print "item: " + mlist[i]
# #mstr = mlist[len(mlist) - 1 - i]
# #mstr = mstr.strip()
# if (mstr.__contains__(" ")):
# if debug:
# print "found: " + mstr.partition(" ")[0]
# deps.append(mstr.partition(" ")[0])
# break
return deps
def get_list_of_dependencies(self, filename, debug=False):
deps = []
if debug:
print "input file: " + filename
#filename needs to be a verilog file
if (filename.partition(".")[2] != "v"):
if debug:
print "File is not a recognized verilog source"
return False
fbuf = ""
#the name is a verilog file, try and open is
try:
filein = open(filename)
fbuf = filein.read()
filein.close()
except IOError as err:
#if debug:
# print "the file is not a full path... searching RTL"
#didn't find with full path, search for it
try:
filepath = saputils.find_rtl_file_location(filename)
filein = open(filepath)
fbuf = filein.read()
filein.close()
except IOError as err_int:
#if debug:
# print "couldn't find file in the RTL directory"
return False
#we have an open file!
if debug:
print "found file!"
#strip out everything we can't use
fbuf = saputils.remove_comments(fbuf)
include_fbuf = fbuf
#search for `include
while (not len(include_fbuf.partition("`include")[2]) == 0):
ifile_name = include_fbuf.partition("`include")[2]
ifile_name = ifile_name.splitlines()[0]
ifile_name = ifile_name.strip()
ifile_name = ifile_name.strip("\"")
print "\t\tfound an include " + ifile_name + " ",
if (not self.verilog_dependency_list.__contains__(ifile_name) and
not self.verilog_file_list.__contains__(ifile_name)):
self.verilog_dependency_list.append(ifile_name)
if debug:
print "adding " + ifile_name + " to the dependency list"
else:
print "... already in have it"
include_fbuf = include_fbuf.partition("`include")[2]
#remove the ports list and the module name
fbuf = fbuf.partition(")")[2]
#modules have lines that start with a '.'
str_list = fbuf.splitlines()
module_token = ""
done = False
while (not done):
for i in range (0, len(str_list)):
line = str_list[i]
#remove white spaces
line = line.strip()
if (line.startswith(".") and line.endswith(",")):
#if debug:
# print "found a possible module... with token: " + line
module_token = line
break
#check if we reached the last line
if (i >= len(str_list) - 1):
done = True
if (not done):
#found a possible module
#partitoin the fbuf
#if debug:
# print "module token " + module_token
module_string = fbuf.partition(module_token)[0]
fbuf = fbuf.partition(module_token)[2]
fbuf = fbuf.partition(";")[2]
str_list = fbuf.splitlines()
#get rid of everything before the possible module
while (len(module_string.partition(";")[2]) > 0):
module_string = module_string.partition(";")[2]
module_string = module_string.partition("(")[0]
module_string = module_string.strip("#")
module_string = module_string.strip()
m_name = module_string.partition(" ")[0]
if debug:
print "module name: " + m_name
if (not deps.__contains__(m_name)):
print "adding it to the deps list"
deps.append(module_string.partition(" ")[0])
#mlist = module_string.splitlines()
#work backwords
#look for the last line that has a '('
#for i in range (0, len(mlist)):
# mstr = mlist[i]
# print "item: " + mlist[i]
# #mstr = mlist[len(mlist) - 1 - i]
# #mstr = mstr.strip()
# if (mstr.__contains__(" ")):
# if debug:
# print "found: " + mstr.partition(" ")[0]
# deps.append(mstr.partition(" ")[0])
# break
return deps
def gen_script(self, tags={}, buf="", debug=False):
"""Overridden function"""
mem_list = []
template = Template(buf)
port_buf = ""
port_def_buf = ""
mem_select_buf = ""
assign_buf = ""
data_block_buf = ""
ack_block_buf = ""
int_block_buf = ""
param_buf = ""
#start with 1 to account for DRT
num_mems = 0
if (tags.has_key("MEMORY")):
#got a list of all the slaves to add to make room for
mem_list = tags["MEMORY"]
num_mems = num_mems + len(mem_list)
if num_mems == 0:
return ""
if debug:
for key in tags["MEMORY"]:
print key + ":" + str(tags["MEMORY"][key])
slave_keywords = ["DRT_ID", "DRT_FLAGS", "DRT_SIZE"]
mem_offset = 0
#generate the parameters
for i in range(0, num_mems):
key = tags["MEMORY"].keys()[i]
absfilename = saputils.find_rtl_file_location(
tags["MEMORY"][key]["filename"])
slave_tags = saputils.get_module_tags(filename=absfilename,
bus="wishbone",
keywords=slave_keywords)
if debug:
print "slave tags: " + str(slave_tags)
mem_size = slave_tags["keywords"]["DRT_SIZE"].strip()
param_buf = param_buf + "parameter MEM_SEL_" + str(
i) + "\t=\t" + str(i) + ";\n"
param_buf = param_buf + "parameter MEM_OFFSET_" + str(
i) + "\t=\t" + str(mem_offset) + ";\n"
param_buf = param_buf + "parameter MEM_SIZE_" + str(
i) + "\t=\t" + mem_size + ";\n"
mem_offset += atoi(mem_size)
#generate the memory select logic
mem_select_buf = "reg [31:0] mem_select;\n"
mem_select_buf += "\n"
mem_select_buf += "always @(rst or m_adr_i or mem_select) begin\n"
mem_select_buf += "\tif (rst) begin\n"
mem_select_buf += "\t\t//nothing selected\n"
mem_select_buf += "\t\tmem_select <= 32'hFFFFFFFF;\n"
mem_select_buf += "\tend\n"
mem_select_buf += "\telse begin\n"
for i in range(num_mems):
if (i == 0):
mem_select_buf += "\t\tif "
else:
mem_select_buf += "\t\telse if "
mem_select_buf += "((m_adr_i >= MEM_OFFSET_" + str(
i) + ") && (m_adr_i < (MEM_OFFSET_" + str(
i) + " + MEM_SIZE_" + str(i) + "))) begin\n"
mem_select_buf += "\t\t\tmem_select <= MEM_SEL_" + str(i) + ";\n"
mem_select_buf += "\t\tend\n"
mem_select_buf += "\t\telse begin\n"
mem_select_buf += "\t\t\tmem_select <= 32'hFFFFFFFF;\n"
mem_select_buf += "\t\tend\n"
mem_select_buf += "\tend\n"
mem_select_buf += "end\n"
#for i in range ( 0, num_mems):
# print "count: " + str(i)
# ports
for i in range(0, num_mems):
port_buf = port_buf + "\ts" + str(i) + "_we_o,\n"
port_buf = port_buf + "\ts" + str(i) + "_cyc_o,\n"
port_buf = port_buf + "\ts" + str(i) + "_stb_o,\n"
port_buf = port_buf + "\ts" + str(i) + "_sel_o,\n"
port_buf = port_buf + "\ts" + str(i) + "_ack_i,\n"
port_buf = port_buf + "\ts" + str(i) + "_dat_o,\n"
port_buf = port_buf + "\ts" + str(i) + "_dat_i,\n"
port_buf = port_buf + "\ts" + str(i) + "_adr_o,\n"
port_buf = port_buf + "\ts" + str(i) + "_int_i"
if ((num_mems > 0) and (i < num_mems - 1)):
port_buf = port_buf + ",\n"
port_buf = port_buf + "\n\n"
# port defines
for i in range(0, num_mems):
port_def_buf = port_def_buf + "output\t\t\ts" + str(i) + "_we_o;\n"
port_def_buf = port_def_buf + "output\t\t\ts" + str(
i) + "_cyc_o;\n"
port_def_buf = port_def_buf + "output\t\t\ts" + str(
i) + "_stb_o;\n"
port_def_buf = port_def_buf + "output\t[3:0]\t\ts" + str(
i) + "_sel_o;\n"
port_def_buf = port_def_buf + "output\t[31:0]\t\ts" + str(
i) + "_adr_o;\n"
port_def_buf = port_def_buf + "output\t[31:0]\t\ts" + str(
i) + "_dat_o;\n"
port_def_buf = port_def_buf + "input\t[31:0]\t\ts" + str(
i) + "_dat_i;\n"
port_def_buf = port_def_buf + "input\t\t\ts" + str(i) + "_ack_i;\n"
port_def_buf = port_def_buf + "input\t\t\ts" + str(i) + "_int_i;\n"
port_def_buf = port_def_buf + "\n\n"
#assign defines
for i in range(0, num_mems):
assign_buf = assign_buf + "assign s" + str(
i) + "_we_o\t=\t(mem_select == MEM_SEL_" + str(
i) + ") ? m_we_i: 0;\n"
assign_buf = assign_buf + "assign s" + str(
i) + "_stb_o\t=\t(mem_select == MEM_SEL_" + str(
i) + ") ? m_stb_i: 0;\n"
assign_buf = assign_buf + "assign s" + str(
i) + "_sel_o\t=\t(mem_select == MEM_SEL_" + str(
i) + ") ? m_sel_i: 0;\n"
assign_buf = assign_buf + "assign s" + str(
i) + "_cyc_o\t=\t(mem_select == MEM_SEL_" + str(
i) + ") ? m_cyc_i: 0;\n"
assign_buf = assign_buf + "assign s" + str(
i) + "_adr_o\t=\t(mem_select == MEM_SEL_" + str(
i) + ") ? m_adr_i: 0;\n"
assign_buf = assign_buf + "assign s" + str(
i) + "_dat_o\t=\t(mem_select == MEM_SEL_" + str(
i) + ") ? m_dat_i: 0;\n"
assign_buf = assign_buf + "\n"
#data in block
data_block_buf = "//data in from slave\n"
data_block_buf = data_block_buf + "always @ (mem_select"
for i in range(0, num_mems):
data_block_buf = data_block_buf + " or s" + str(i) + "_dat_i"
data_block_buf = data_block_buf + ") begin\n\tcase (mem_select)\n"
for i in range(0, num_mems):
data_block_buf = data_block_buf + "\t\tMEM_SEL_" + str(
i) + ": begin\n\t\t\tm_dat_o <= s" + str(
i) + "_dat_i;\n\t\tend\n"
data_block_buf = data_block_buf + "\t\tdefault: begin\n\t\t\tm_dat_o <= 32\'h0000;\n\t\tend\n\tendcase\nend\n\n"
#ack in block
ack_block_buf = "//ack in from slave\n\n"
ack_block_buf = ack_block_buf + "always @ (mem_select"
for i in range(0, num_mems):
ack_block_buf = ack_block_buf + " or s" + str(i) + "_ack_i"
ack_block_buf = ack_block_buf + ") begin\n\tcase (mem_select)\n"
for i in range(0, num_mems):
ack_block_buf = ack_block_buf + "\t\tMEM_SEL_" + str(
i) + ": begin\n\t\t\tm_ack_o <= s" + str(
i) + "_ack_i;\n\t\tend\n"
ack_block_buf = ack_block_buf + "\t\tdefault: begin\n\t\t\tm_ack_o <= 1\'h0;\n\t\tend\n\tendcase\nend\n\n"
#int in block
int_block_buf = "//int in from slave\n\n"
int_block_buf = int_block_buf + "always @ (mem_select"
for i in range(0, num_mems):
int_block_buf = int_block_buf + " or s" + str(i) + "_int_i"
int_block_buf = int_block_buf + ") begin\n\tcase (mem_select)\n"
for i in range(0, num_mems):
int_block_buf = int_block_buf + "\t\tMEM_SEL_" + str(
i) + ": begin\n\t\t\tm_int_o <= s" + str(
i) + "_int_i;\n\t\tend\n"
int_block_buf = int_block_buf + "\t\tdefault: begin\n\t\t\tm_int_o <= 1\'h0;\n\t\tend\n\tendcase\nend\n\n"
if debug:
print "buf: " + buf
buf = template.substitute(PORTS=port_buf,
PORT_DEFINES=port_def_buf,
MEM_SELECT=mem_select_buf,
ASSIGN=assign_buf,
DATA=data_block_buf,
ACK=ack_block_buf,
INT=int_block_buf,
MEM_PARAMS=param_buf)
if debug:
print "buf: " + buf
return buf
def get_name(self):
print "wishbone_mem_interconnect.py"
def gen_script(self, tags={}, buf="", debug=False):
"""Generate the Top Module"""
board_dict = saputils.get_board_config(tags["board"])
invert_reset = board_dict["invert_reset"]
en_mem_bus = False
slave_list = tags["SLAVES"]
self.internal_bindings = {}
self.bindings = {}
if "MEMORY" in tags:
# if debug:
# print "Found a memory bus"
if (len(tags["MEMORY"]) > 0):
if debug:
print "found " + str(len(
tags["MEMORY"])) + " memory devices"
en_mem_bus = True
num_slaves = len(slave_list) + 1
self.tags = tags
#add the internal bindings
self.internal_bindings = {}
if "internal_bind" in self.tags.keys():
self.internal_bindings = self.tags["internal_bind"]
#print "Internal bindings: %s" % str(self.internal_bindings)
#add the global tags
self.bindings = self.tags["bind"]
#add the interface bindings directly
if "bind" in self.tags["INTERFACE"]:
for if_name in self.tags["INTERFACE"]["bind"]:
self.bindings[if_name] = self.tags["INTERFACE"]["bind"][
if_name]
#add each of the slave items to the binding
#insert the names
for slave_name in self.tags["SLAVES"]:
if "bind" in self.tags["SLAVES"][slave_name]:
for bind_name in self.tags["SLAVES"][slave_name]["bind"]:
self.bindings[slave_name + "_" + bind_name] = self.tags[
"SLAVES"][slave_name]["bind"][bind_name]
if "MEMORY" in self.tags:
#add the slave bindings to the list
for mem_name in self.tags["MEMORY"]:
if "bind" in self.tags["MEMORY"][mem_name]:
for bind_name in self.tags["MEMORY"][mem_name]["bind"]:
self.bindings[mem_name + "_" + bind_name] = self.tags[
"MEMORY"][mem_name]["bind"][bind_name]
if debug:
print "found " + str(len(slave_list)) + " slaves"
for slave in slave_list:
print slave
#remove all the ports from the possible wires
self.add_ports_to_wires()
template = Template(buf)
header = ""
port_buf = self.generate_ports()
arb_buf = self.generate_arbitrator_buffer()
wr_buf = ""
wi_buf = ""
wmi_buf = ""
wm_buf = ""
footer = ""
header = "module top (\n"
#header = header + "\tclk_in,\n"
header = header + "\tclk,\n"
header = header + "\trst,\n"
for c_index in range(0, len(self.bindings.keys())):
name = self.bindings.keys()[c_index]
header = header + "\t" + self.bindings[name]["port"]
if (c_index < len(self.bindings.keys()) - 1):
header = header + ","
header = header + "\n"
header = header + ");"
footer = "endmodule"
#declare the ports
#in the future utilize the constraints to generate the connections
#declare the wires
wr_buf = wr_buf + "\t//input handler signals\n"
#wr_buf = wr_buf + "\tinput\t\tclk_in;\n"
wr_buf = wr_buf + "\tinput\t\t\tclk;\n"
#wr_buf = wr_buf + "\twire\t\tclk;\n"
self.wires.append("clk")
#self.wires.append("clk_in")
wr_buf = wr_buf + "\tinput\t\t\trst;\n"
self.wires.append("rst")
if invert_reset:
#print "found invert reset!"
wr_buf += "\twire\t\t\trst_n;\n"
self.wires.append("rst_n")
wr_buf = wr_buf + "\twire\t[31:0]\tin_command;\n"
self.wires.append("in_command")
wr_buf = wr_buf + "\twire\t[31:0]\tin_address;\n"
self.wires.append("in_address")
wr_buf = wr_buf + "\twire\t[31:0]\tin_data;\n"
self.wires.append("in_data")
wr_buf = wr_buf + "\twire\t[27:0]\tin_data_count;\n"
self.wires.append("in_data_count")
wr_buf = wr_buf + "\twire\t\t\tih_ready;\n\n"
self.wires.append("ih_ready")
wr_buf = wr_buf + "\twire\t\t\tih_reset;\n\n"
self.wires.append("ih_reset")
wr_buf = wr_buf + "\t//output handler signals\n"
wr_buf = wr_buf + "\twire\t[31:0]\tout_status;\n"
self.wires.append("out_status")
wr_buf = wr_buf + "\twire\t[31:0]\tout_address;\n"
self.wires.append("out_address")
wr_buf = wr_buf + "\twire\t[31:0]\tout_data;\n"
self.wires.append("out_data")
wr_buf = wr_buf + "\twire\t[27:0]\tout_data_count;\n"
self.wires.append("out_data_count")
wr_buf = wr_buf + "\twire\t\t\toh_ready;\n"
self.wires.append("oh_ready")
wr_buf = wr_buf + "\twire\t\t\toh_en;\n\n"
self.wires.append("oh_en")
wr_buf = wr_buf + "\t//master signals\n"
wr_buf = wr_buf + "\twire\t\t\tmaster_ready;\n"
self.wires.append("master_ready")
wr_buf = wr_buf + "\twire\t\t\twbm_we_o;\n"
self.wires.append("wbm_we_o")
wr_buf = wr_buf + "\twire\t\t\twbm_cyc_o;\n"
self.wires.append("wbm_cyc_o")
wr_buf = wr_buf + "\twire\t\t\twbm_stb_o;\n"
self.wires.append("wbm_stb_o")
wr_buf = wr_buf + "\twire\t[3:0]\twbm_sel_o;\n"
self.wires.append("wbm_sel_o")
wr_buf = wr_buf + "\twire\t[31:0]\twbm_adr_o;\n"
self.wires.append("wbm_adr_o")
wr_buf = wr_buf + "\twire\t[31:0]\twbm_dat_i;\n"
self.wires.append("wbm_dat_i")
wr_buf = wr_buf + "\twire\t[31:0]\twbm_dat_o;\n"
self.wires.append("wbm_dat_o")
wr_buf = wr_buf + "\twire\t\t\twbm_ack_i;\n"
self.wires.append("wbm_ack_i")
wr_buf = wr_buf + "\twire\t\t\twbm_int_i;\n\n"
self.wires.append("wbm_int_i")
wr_buf = wr_buf + "\twire\t\t\tmem_we_o;\n"
self.wires.append("mem_we_o")
wr_buf = wr_buf + "\twire\t\t\tmem_cyc_o;\n"
self.wires.append("mem_cyc_o")
wr_buf = wr_buf + "\twire\t\t\tmem_stb_o;\n"
self.wires.append("mem_stb_o")
wr_buf = wr_buf + "\twire\t[3:0]\tmem_sel_o;\n"
self.wires.append("mem_sel_o")
wr_buf = wr_buf + "\twire\t[31:0]\tmem_adr_o;\n"
self.wires.append("mem_adr_o")
wr_buf = wr_buf + "\twire\t[31:0]\tmem_dat_i;\n"
self.wires.append("mem_dat_i")
wr_buf = wr_buf + "\twire\t[31:0]\tmem_dat_o;\n"
self.wires.append("mem_dat_o")
wr_buf = wr_buf + "\twire\t\t\tmem_ack_i;\n"
self.wires.append("mem_ack_i")
wr_buf = wr_buf + "\twire\t\t\tmem_int_i;\n"
self.wires.append("mem_int_i")
wr_buf = wr_buf + "\twire\t[31:0]\twbm_debug_out;\n\n"
self.wires.append("wbm_debug_out")
#put the in clock on the global buffer
#wr_buf = wr_buf + "\t//add a global clock buffer to the input clock\n"
#wr_buf = wr_buf + "\tIBUFG clk_ibuf(.I(clk_in), .O(clk));\n\n"
wr_buf = wr_buf + "\t//slave signals\n\n"
for i in range(0, num_slaves):
wr_buf = wr_buf + "\t//slave " + str(i) + "\n"
wr_buf = wr_buf + "\twire\t\t\ts" + str(i) + "_wbs_we_i;\n"
self.wires.append("s" + str(i) + "_wbs_we_i")
wr_buf = wr_buf + "\twire\t\t\ts" + str(i) + "_wbs_cyc_i;\n"
self.wires.append("s" + str(i) + "_wbs_cyc_i")
wr_buf = wr_buf + "\twire\t[31:0]\ts" + str(i) + "_wbs_dat_i;\n"
self.wires.append("s" + str(i) + "_wbs_dat_i")
wr_buf = wr_buf + "\twire\t[31:0]\ts" + str(i) + "_wbs_dat_o;\n"
self.wires.append("s" + str(i) + "_wbs_dat_o")
wr_buf = wr_buf + "\twire\t[31:0]\ts" + str(i) + "_wbs_adr_i;\n"
self.wires.append("s" + str(i) + "_wbs_adr_i")
wr_buf = wr_buf + "\twire\t\t\ts" + str(i) + "_wbs_stb_i;\n"
self.wires.append("s" + str(i) + "_wbs_stb_i")
wr_buf = wr_buf + "\twire\t[3:0]\ts" + str(i) + "_wbs_sel_i;\n"
self.wires.append("s" + str(i) + "_wbs_sel_i")
wr_buf = wr_buf + "\twire\t\t\ts" + str(i) + "_wbs_ack_o;\n"
self.wires.append("s" + str(i) + "_wbs_ack_o")
wr_buf = wr_buf + "\twire\t\t\ts" + str(i) + "_wbs_int_o;\n\n"
self.wires.append("s" + str(i) + "_wbs_int_o")
if (en_mem_bus):
for i in range(0, len(tags["MEMORY"])):
wr_buf = wr_buf + "\t//mem slave " + str(i) + "\n"
wr_buf = wr_buf + "\twire\t\t\tsm" + str(i) + "_wbs_we_i;\n"
self.wires.append("sm" + str(i) + "_wbs_we_i")
wr_buf = wr_buf + "\twire\t\t\tsm" + str(i) + "_wbs_cyc_i;\n"
self.wires.append("sm" + str(i) + "_wbs_cyc_i")
wr_buf = wr_buf + "\twire\t[31:0]\tsm" + str(
i) + "_wbs_dat_i;\n"
self.wires.append("sm" + str(i) + "_wbs_dat_i")
wr_buf = wr_buf + "\twire\t[31:0]\tsm" + str(
i) + "_wbs_dat_o;\n"
self.wires.append("sm" + str(i) + "_wbs_dat_o")
wr_buf = wr_buf + "\twire\t[31:0]\tsm" + str(
i) + "_wbs_adr_i;\n"
self.wires.append("sm" + str(i) + "_wbs_adr_i")
wr_buf = wr_buf + "\twire\t\t\tsm" + str(i) + "_wbs_stb_i;\n"
self.wires.append("sm" + str(i) + "_wbs_stb_i")
wr_buf = wr_buf + "\twire\t[3:0]\tsm" + str(
i) + "_wbs_sel_i;\n"
self.wires.append("sm" + str(i) + "_wbs_sel_i")
wr_buf = wr_buf + "\twire\t\t\tsm" + str(i) + "_wbs_ack_o;\n"
self.wires.append("sm" + str(i) + "_wbs_ack_o")
wr_buf = wr_buf + "\twire\t\t\tsm" + str(i) + "_wbs_int_o;\n\n"
self.wires.append("sm" + str(i) + "_wbs_int_o")
if debug:
print "wr_buf: \n" + wr_buf
#generate the IO handler
io_filename = tags["INTERFACE"]["filename"]
absfilepath = saputils.find_rtl_file_location(io_filename)
io_tags = saputils.get_module_tags(filename=absfilepath,
bus="wishbone")
io_buf = self.generate_buffer(name="io",
module_tags=io_tags,
io_module=True)
#for the FPGA
#constraints can be a dictionary with the mappings from device
#to input/output/inout multidimensional values
#this should just be file with text that I can pull in, it will always be
#the same!
#instantiate the connection interface
#should this be another script that is clled within here?
#can I extrapolate the required information directly from the
#file?
#interconnect
wi_buf = "\twishbone_interconnect wi (\n"
wi_buf = wi_buf + "\t\t.clk(clk),\n"
if invert_reset:
wi_buf = wi_buf + "\t\t.rst(rst_n),\n\n"
else:
wi_buf = wi_buf + "\t\t.rst(rst),\n\n"
wi_buf = wi_buf + "\t\t//master\n"
wi_buf = wi_buf + "\t\t.m_we_i(wbm_we_o),\n"
wi_buf = wi_buf + "\t\t.m_cyc_i(wbm_cyc_o),\n"
wi_buf = wi_buf + "\t\t.m_stb_i(wbm_stb_o),\n"
wi_buf = wi_buf + "\t\t.m_sel_i(wbm_sel_o),\n"
wi_buf = wi_buf + "\t\t.m_ack_o(wbm_ack_i),\n"
wi_buf = wi_buf + "\t\t.m_dat_i(wbm_dat_o),\n"
wi_buf = wi_buf + "\t\t.m_dat_o(wbm_dat_i),\n"
wi_buf = wi_buf + "\t\t.m_adr_i(wbm_adr_o),\n"
wi_buf = wi_buf + "\t\t.m_int_o(wbm_int_i),\n\n"
for i in range(0, num_slaves):
wi_buf = wi_buf + "\t\t//slave " + str(i) + "\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_we_o (s" + str(
i) + "_wbs_we_i),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_cyc_o(s" + str(
i) + "_wbs_cyc_i),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_stb_o(s" + str(
i) + "_wbs_stb_i),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_sel_o(s" + str(
i) + "_wbs_sel_i),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_ack_i(s" + str(
i) + "_wbs_ack_o),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_dat_o(s" + str(
i) + "_wbs_dat_i),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_dat_i(s" + str(
i) + "_wbs_dat_o),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_adr_o(s" + str(
i) + "_wbs_adr_i),\n"
wi_buf = wi_buf + "\t\t.s" + str(i) + "_int_i(s" + str(
i) + "_wbs_int_o)"
if (i < num_slaves - 1):
wi_buf = wi_buf + ",\n"
wi_buf = wi_buf + "\n\n"
wi_buf = wi_buf + "\t);"
if debug:
print "wi_buf: \n" + wi_buf
#memory interconnect
if en_mem_bus:
if debug:
print "make the membus"
wmi_buf = "\twishbone_mem_interconnect wmi (\n"
wmi_buf = wmi_buf + "\t\t.clk(clk),\n"
if invert_reset:
wmi_buf = wmi_buf + "\t\t.rst(rst_n),\n\n"
else:
wmi_buf = wmi_buf + "\t\t.rst(rst),\n\n"
wmi_buf = wmi_buf + "\t\t//master\n"
wmi_buf = wmi_buf + "\t\t.m_we_i(mem_we_o),\n"
wmi_buf = wmi_buf + "\t\t.m_cyc_i(mem_cyc_o),\n"
wmi_buf = wmi_buf + "\t\t.m_stb_i(mem_stb_o),\n"
wmi_buf = wmi_buf + "\t\t.m_sel_i(mem_sel_o),\n"
wmi_buf = wmi_buf + "\t\t.m_ack_o(mem_ack_i),\n"
wmi_buf = wmi_buf + "\t\t.m_dat_i(mem_dat_o),\n"
wmi_buf = wmi_buf + "\t\t.m_dat_o(mem_dat_i),\n"
wmi_buf = wmi_buf + "\t\t.m_adr_i(mem_adr_o),\n"
wmi_buf = wmi_buf + "\t\t.m_int_o(mem_int_i),\n\n"
num_mems = len(tags["MEMORY"])
for i in range(0, num_mems):
wmi_buf = wmi_buf + "\t//mem slave " + str(i) + "\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_we_o(sm" + str(
i) + "_wbs_we_i),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_cyc_o(sm" + str(
i) + "_wbs_cyc_i),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_stb_o(sm" + str(
i) + "_wbs_stb_i),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_sel_o(sm" + str(
i) + "_wbs_sel_i),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_ack_i(sm" + str(
i) + "_wbs_ack_o),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_dat_o(sm" + str(
i) + "_wbs_dat_i),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_dat_i(sm" + str(
i) + "_wbs_dat_o),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_adr_o(sm" + str(
i) + "_wbs_adr_i),\n"
wmi_buf = wmi_buf + "\t\t.s" + str(i) + "_int_i(sm" + str(
i) + "_wbs_int_o)"
if ((num_mems > 0) and (i < num_mems - 1)):
wmi_buf = wmi_buf + ",\n"
wmi_buf = wmi_buf + "\n\n"
wmi_buf = wmi_buf + "\t);"
if debug:
print "wmi_buf: \n" + wmi_buf
#instantiate the io handler
#instantiate the master
wm_buf = wm_buf + "\twishbone_master wm (\n"
wm_buf = wm_buf + "\t\t.clk(clk),\n"
if invert_reset:
wm_buf = wm_buf + "\t\t.rst(rst_n),\n\n"
else:
wm_buf = wm_buf + "\t\t.rst(rst),\n\n"
wm_buf = wm_buf + "\t\t//input handler signals\n"
wm_buf = wm_buf + "\t\t.in_ready(ih_ready),\n"
wm_buf = wm_buf + "\t\t.ih_reset(ih_reset),\n"
wm_buf = wm_buf + "\t\t.in_command(in_command),\n"
wm_buf = wm_buf + "\t\t.in_address(in_address),\n"
wm_buf = wm_buf + "\t\t.in_data(in_data),\n"
wm_buf = wm_buf + "\t\t.in_data_count(in_data_count),\n\n"
wm_buf = wm_buf + "\t\t//output handler signals\n"
wm_buf = wm_buf + "\t\t.out_ready(oh_ready),\n"
wm_buf = wm_buf + "\t\t.out_en(oh_en),\n"
wm_buf = wm_buf + "\t\t.out_status(out_status),\n"
wm_buf = wm_buf + "\t\t.out_address(out_address),\n"
wm_buf = wm_buf + "\t\t.out_data(out_data),\n"
wm_buf = wm_buf + "\t\t.out_data_count(out_data_count),\n"
wm_buf = wm_buf + "\t\t.master_ready(master_ready),\n\n"
wm_buf = wm_buf + "\t\t//interconnect signals\n"
wm_buf = wm_buf + "\t\t.wb_adr_o(wbm_adr_o),\n"
wm_buf = wm_buf + "\t\t.wb_dat_o(wbm_dat_o),\n"
wm_buf = wm_buf + "\t\t.wb_dat_i(wbm_dat_i),\n"
wm_buf = wm_buf + "\t\t.wb_stb_o(wbm_stb_o),\n"
wm_buf = wm_buf + "\t\t.wb_cyc_o(wbm_cyc_o),\n"
wm_buf = wm_buf + "\t\t.wb_we_o(wbm_we_o),\n"
wm_buf = wm_buf + "\t\t.wb_msk_o(wbm_msk_o),\n"
wm_buf = wm_buf + "\t\t.wb_sel_o(wbm_sel_o),\n"
wm_buf = wm_buf + "\t\t.wb_ack_i(wbm_ack_i),\n"
wm_buf = wm_buf + "\t\t.wb_int_i(wbm_int_i),\n\n"
wm_buf = wm_buf + "\t\t//memory interconnect signals\n"
wm_buf = wm_buf + "\t\t.mem_adr_o(mem_adr_o),\n"
wm_buf = wm_buf + "\t\t.mem_dat_o(mem_dat_o),\n"
wm_buf = wm_buf + "\t\t.mem_dat_i(mem_dat_i),\n"
wm_buf = wm_buf + "\t\t.mem_stb_o(mem_stb_o),\n"
wm_buf = wm_buf + "\t\t.mem_cyc_o(mem_cyc_o),\n"
wm_buf = wm_buf + "\t\t.mem_we_o(mem_we_o),\n"
wm_buf = wm_buf + "\t\t.mem_msk_o(mem_msk_o),\n"
wm_buf = wm_buf + "\t\t.mem_sel_o(mem_sel_o),\n"
wm_buf = wm_buf + "\t\t.mem_ack_i(mem_ack_i),\n"
wm_buf = wm_buf + "\t\t.mem_int_i(mem_int_i),\n\n"
wm_buf = wm_buf + "\t\t.debug_out(wbm_debug_out)\n\n"
wm_buf = wm_buf + "\t);"
if debug:
print "wm_buf: \n" + wm_buf
#Arbitrators
#Slaves
slave_index = 0
slave_buffer_list = []
absfilename = saputils.find_rtl_file_location("device_rom_table.v")
slave_tags = saputils.get_module_tags(filename=absfilename,
bus="wishbone")
slave_buf = self.generate_buffer(name="drt",
index=0,
module_tags=slave_tags)
slave_buffer_list.append(slave_buf)
for i in range(0, len(tags["SLAVES"])):
slave_name = tags["SLAVES"].keys()[i]
slave = tags["SLAVES"][slave_name]["filename"]
if debug:
print "Slave name: " + slave
absfilename = saputils.find_rtl_file_location(slave)
slave_tags = saputils.get_module_tags(filename=absfilename,
bus="wishbone")
slave_buf = self.generate_buffer(name=slave_name,
index=i + 1,
module_tags=slave_tags)
slave_buffer_list.append(slave_buf)
#Memory devices
mem_buf = ""
mem_buffer_list = []
if en_mem_bus:
#need to make all the memory devices for the memory bus
mem_index = 0
mem_buffer_list = []
for i in range(0, len(tags["MEMORY"])):
mem_name = tags["MEMORY"].keys()[i]
filename = tags["MEMORY"][mem_name]["filename"]
if debug:
print "Mem device: " + mem_name + ", mem file: " + filename
absfilename = saputils.find_rtl_file_location(filename)
mem_tags = saputils.get_module_tags(filename=absfilename,
bus="wishbone")
mem_buf = self.generate_buffer(name=mem_name,
index=i,
module_tags=mem_tags,
mem_slave=True)
mem_buffer_list.append(mem_buf)
buf_bind = ""
buf_bind += "\t//assigns\n"
#Generate the internal bindings
if (len(self.internal_bindings.keys()) > 0):
buf_bind += "\t//Internal Bindings\n"
for key in self.internal_bindings.keys():
buf_bind += "\tassign\t%s\t=\t%s;\n" % (
key, self.internal_bindings[key]["signal"])
#Generate the external bindings
if (len(self.bindings.keys()) > 0):
buf_bind += "\t//Bindings to Ports\n"
for key in self.bindings.keys():
if (self.bindings[key]["direction"] == "input"):
buf_bind = buf_bind + "\tassign\t" + key + "\t=\t" + self.bindings[
key]["port"] + ";\n"
elif (self.bindings[key]["direction"] == "output"):
buf_bind = buf_bind + "\tassign\t" + self.bindings[key][
"port"] + "\t=\t" + key + ";\n"
if invert_reset:
buf_bind += "\tassign\trst_n\t\t=\t~rst;\n"
top_buffer = header + "\n\n"
top_buffer += port_buf + "\n\n"
top_buffer += wr_buf + "\n\n"
top_buffer += io_buf + "\n\n"
top_buffer += wi_buf + "\n\n"
top_buffer += wmi_buf + "\n\n"
if (len(arb_buf) > 0):
top_buffer += arb_buf + "\n\n"
top_buffer += wm_buf + "\n\n"
for slave_buf in slave_buffer_list:
top_buffer = top_buffer + "\n\n" + slave_buf
for mem_buf in mem_buffer_list:
top_buffer = top_buffer + "\n\n" + mem_buf
top_buffer = top_buffer + "\n\n" + buf_bind + "\n\n" + footer
return top_buffer