def get_snap_coarse_fft(c, fpgas=[], pol=0, setup_snap=True):
"""
Read and return data from the coarse FFT.
Returns a list of the data from only that polarisation.
"""
if len(fpgas) == 0:
fpgas = c.ffpgas
if setup_snap:
corr_functions.write_masked_register(
fpgas,
register_fengine_control,
debug_snap_select=snap_fengine_debug_select['coarse_72'])
corr_functions.write_masked_register(fpgas,
register_fengine_coarse_control,
debug_pol_select=pol,
debug_specify_chan=0)
snap_data = snap.snapshots_get(fpgas=fpgas,
dev_names=snap_debug,
wait_period=3)
rd = []
for ctr in range(0, len(snap_data['data'])):
d = snap_data['data'][ctr]
repeater = construct.GreedyRepeater(snap_fengine_debug_coarse_fft)
up = repeater.parse(d)
coarsed = []
for a in up:
for b in range(0, 2):
num = bin2fp(a['d%i_r' % b], 18,
17) + (1j * bin2fp(a['d%i_i' % b], 18, 17))
coarsed.append(num)
rd.append(coarsed)
return rd
def get_snap_ct(c, fpgas = [], offset = -1, setup_snap = True):
"""
Read and return data from the corner turner. Both pols are returned.
"""
if len(fpgas) == 0:
fpgas = c.ffpgas
if setup_snap:
corr_functions.write_masked_register(fpgas, register_fengine_control, debug_snap_select = snap_fengine_debug_select['ct_64'])
snap_data = snap.snapshots_get(fpgas = fpgas, dev_names = snap_debug, wait_period = 3, offset = offset)
rd = []
for ctr in range(0, len(snap_data['data'])):
d = snap_data['data'][ctr]
repeater = construct.GreedyRepeater(snap_fengine_debug_ct)
up = repeater.parse(d)
fdata_p0 = []
fdata_p1 = []
for a in up:
p0 = []
p1 = []
p0.append(bin2fp(a['p00_r'], 4, 3) + (1j * bin2fp(a['p00_i'], 4, 3)))
p0.append(bin2fp(a['p01_r'], 4, 3) + (1j * bin2fp(a['p01_i'], 4, 3)))
p0.append(bin2fp(a['p02_r'], 4, 3) + (1j * bin2fp(a['p02_i'], 4, 3)))
p0.append(bin2fp(a['p03_r'], 4, 3) + (1j * bin2fp(a['p03_i'], 4, 3)))
p1.append(bin2fp(a['p10_r'], 4, 3) + (1j * bin2fp(a['p10_i'], 4, 3)))
p1.append(bin2fp(a['p11_r'], 4, 3) + (1j * bin2fp(a['p11_i'], 4, 3)))
p1.append(bin2fp(a['p12_r'], 4, 3) + (1j * bin2fp(a['p12_i'], 4, 3)))
p1.append(bin2fp(a['p13_r'], 4, 3) + (1j * bin2fp(a['p13_i'], 4, 3)))
fdata_p0.extend(p0)
fdata_p1.extend(p1)
rd.append([fdata_p0, fdata_p1])
return rd
def get_snap_adc_DUMB(c, fpgas=[], wait_period=3):
"""
Read raw samples from the ADC snap block.
2 pols, each one 4 parallel samples f8.7. So 64-bits total.
"""
raw = snap.snapshots_get(fpgas=fpgas,
dev_names=snap_adc,
wait_period=wait_period)
repeater = construct.GreedyRepeater(snap_fengine_adc)
rv = []
for index, d in enumerate(raw['data']):
data = [[], []]
od = numpy.fromstring(d, dtype=numpy.int8)
for ctr in range(0, len(od), 8):
for ctr2 in range(0, 4):
data[0].append(od[ctr + ctr2])
for ctr2 in range(4, 8):
data[1].append(od[ctr + ctr2])
data = [
numpy.array(data[0], dtype=numpy.int8),
numpy.array(data[1], dtype=numpy.int8)
]
v = {'fpga_index': index, 'data': data}
rv.append(v)
return rv
def get_snap_fine_fft(c, fpgas=[], offset=-1, setup_snap=True):
if len(fpgas) == 0:
fpgas = c.ffpgas
if setup_snap:
corr_functions.write_masked_register(
fpgas,
register_fengine_control,
debug_snap_select=snap_fengine_debug_select['fine_128'])
snap_data = snap.snapshots_get(fpgas=fpgas,
dev_names=snap_debug,
wait_period=3,
offset=offset)
rd = []
for ctr in range(0, len(snap_data['data'])):
d = snap_data['data'][ctr]
repeater = construct.GreedyRepeater(snap_fengine_debug_fine_fft)
up = repeater.parse(d)
fdata_p0 = []
fdata_p1 = []
for a in up:
p0c = bin2fp(a['p0_r'], fine_fft_bitwidth,
17) + (1j * bin2fp(a['p0_i'], fine_fft_bitwidth, 17))
p1c = bin2fp(a['p1_r'], fine_fft_bitwidth,
17) + (1j * bin2fp(a['p1_i'], fine_fft_bitwidth, 17))
fdata_p0.append(p0c)
fdata_p1.append(p1c)
rd.append([fdata_p0, fdata_p1])
return rd
def get_snap_coarse_channel(c, fpgas = [], pol = 0, channel = -1, setup_snap = True):
"""
Get data from a specific coarse channel - straight out of the FFT into the snap block, NOT via the buffer block.
Returns a list of the data from only that polarisation.
"""
if channel == -1:
raise RuntimeError('Cannot get data from unspecified channel.')
if len(fpgas) == 0:
fpgas = c.ffpgas
if setup_snap:
corr_functions.write_masked_register(fpgas, register_fengine_control, debug_snap_select = snap_fengine_debug_select['coarse_72'])
corr_functions.write_masked_register(fpgas, register_fengine_coarse_control, debug_pol_select = pol, debug_specify_chan = 1, debug_chan = channel >> 1)
snap_data = snap.snapshots_get(fpgas = fpgas, dev_names = snap_debug, wait_period = 3)
rd = []
for ctr in range(0, len(snap_data['data'])):
d = snap_data['data'][ctr]
repeater = construct.GreedyRepeater(snap_fengine_debug_coarse_fft)
up = repeater.parse(d)
coarsed = []
for a in up:
if channel & 1:
num = bin2fp(a['d1_r'], 18, 17) + (1j * bin2fp(a['d1_i'], 18, 17))
else:
num = bin2fp(a['d0_r'], 18, 17) + (1j * bin2fp(a['d0_i'], 18, 17))
coarsed.append(num)
rd.append(coarsed)
return rd
def get_snap_feng_10gbe(c,
fpgas=[],
offset=-1,
man_trigger=False,
man_valid=False):
if len(fpgas) == 0:
fpgas = c.ffpgas
corr_functions.write_masked_register(
fpgas,
register_fengine_control,
debug_snap_select=snap_fengine_debug_select['gbetx0_128'])
snap_data = snap.snapshots_get(fpgas=fpgas,
dev_names=snap_debug,
wait_period=3,
offset=offset,
man_trig=man_trigger,
man_valid=man_valid,
circular_capture=False)
rd = []
for ctr in range(0, len(snap_data['data'])):
d = snap_data['data'][ctr]
repeater = construct.GreedyRepeater(snap_fengine_gbe_tx)
up = repeater.parse(d)
for a in up:
a['link_down'] = not a['link_up']
a['hdr_valid'] = False
a['mrst'] = False
a['sync'] = False
rd.append(up)
return rd
def get_snap_buffer_pfb(c, fpgas=[], pol=0, setup_snap=True, pfb=False):
'''This DOESN'T EXIST in regular F-engines. Only in specific debug versions.
'''
if len(fpgas) == 0:
fpgas = c.ffpgas
if setup_snap:
if pfb:
corr_functions.write_masked_register(
fpgas,
register_fengine_control,
debug_snap_select=snap_fengine_debug_select['pfb_72'])
else:
corr_functions.write_masked_register(
fpgas,
register_fengine_control,
debug_snap_select=snap_fengine_debug_select['buffer_72'])
corr_functions.write_masked_register(fpgas,
register_fengine_coarse_control,
debug_pol_select=pol)
snap_data = snap.snapshots_get(fpgas=fpgas,
dev_names=snap_debug,
wait_period=3)
rd = []
for ctr in range(0, len(snap_data['data'])):
d = snap_data['data'][ctr]
repeater = construct.GreedyRepeater(snap_fengine_debug_coarse_fft)
up = repeater.parse(d)
coarsed = []
for a in up:
num = bin2fp(a['d%i_r' % pol], 18,
17) + (1j * bin2fp(a['d%i_i' % pol], 18, 17))
coarsed.append(num)
rd.append(coarsed)
return rd
def DONE_get_ct_snap(correlator, offset=-1):
corr_functions.write_masked_register(correlator.ffpgas,
register_fengine_fine_control,
quant_snap_select=2)
raw = snap.snapshots_get(correlator.ffpgas,
dev_names=fine_snap_name,
man_trig=False,
man_valid=False,
wait_period=3,
offset=offset,
circular_capture=False)
chan_values = []
for index, d in enumerate(raw['data']):
up = list(struct.unpack('>%iI' % (len(d) / 4), d))
values = [[], []]
for value in up:
# two freq channel values for the same freq-channel, both pols
# will have to use the offset to get multiple freq channels
p00 = value >> 24
p10 = (value >> 16) & 0xff
p01 = (value >> 8) & 0xff
p11 = value & 0xff
def extract8bit(v8):
r = (v8 & ((2**8) - (2**4))) >> 4
i = (v8 & ((2**4) - (2**0)))
return r + (1j * i)
values[0].append(value >> 24)
values[0].append((value >> 8) & 0xff)
values[1].append((value >> 16) & 0xff)
values[1].append(value & 0xff)
chan_values.append({'fpga_index': index, 'data': values})
return chan_values
def get_snap_xaui(c, fpgas = [], offset = -1, man_trigger = False, man_valid = False, wait_period = 3):
"""
Read the XAUI data out of the general debug snap block.
"""
if len(fpgas) == 0:
fpgas = c.ffpgas
corr_functions.write_masked_register(fpgas, register_fengine_control, debug_snap_select = snap_fengine_debug_select['xaui_128'])
snap_data = snap.snapshots_get(fpgas = fpgas, dev_names = snap_debug, wait_period = wait_period, offset = offset, man_trig = man_trigger, man_valid = man_valid, circular_capture = False)
return snap_data
def _fpga_snap_quant(fpga=None, offset=-1, wbc_compat=False, debug_data=None):
''''
Get quantiser snap data from only one f-engine FPGA.
NB: Assumes the quantiser has already been selected in the control register.
Returns a snapshot of quantised data in one of two formats, depending on the wbc_compat argument.
Either way, it's data for both pols.
debug_data is data from the snap.snapshots_get function
'''
def _log(msg):
fpga._logger.debug('_fpga_snap_quant: %s' % msg)
if fpga == None:
raise RuntimeError(
'Please provide the FPGA from which to read the quantised data.')
if debug_data == None:
_log('reading snap data at offset %i.' % offset)
snap_data = snap.snapshots_get(fpgas=[fpga],
dev_names=snap_debug,
wait_period=3,
offset=offset)['data'][0]
else:
_log('using debug data, not fresh snap data.')
snap_data = debug_data['data'][0]
_log('unpacking data.')
data = [[], []]
if not wbc_compat:
repeater = construct.GreedyRepeater(snap_fengine_debug_quant)
unpacked = repeater.parse(snap_data)
for ctr in unpacked:
p0c = bin2fp(ctr['p0_r'], 4, 3) + (1j * bin2fp(ctr['p0_i'], 4, 3))
p1c = bin2fp(ctr['p1_r'], 4, 3) + (1j * bin2fp(ctr['p1_i'], 4, 3))
data[0].append(p0c)
data[1].append(p1c)
else:
# remember that the data is 16-bit padded up to 128-bit because of the one debug snap block, so only 2 of every 16 bytes are valid data
unpacked = numpy.fromstring(snap_data, dtype=numpy.uint8)
for ctr in range(14, len(unpacked), 16):
pol0_r_bits = (unpacked[ctr] & ((2**8) - (2**4))) >> 4
pol0_i_bits = (unpacked[ctr] & ((2**4) - (2**0)))
pol1_r_bits = (unpacked[ctr + 1] & ((2**8) - (2**4))) >> 4
pol1_i_bits = (unpacked[ctr + 1] & ((2**4) - (2**0)))
data[0].append(
float(((numpy.int8(pol0_r_bits << 4) >> 4))) +
(1j * float(((numpy.int8(pol0_i_bits << 4) >> 4)))))
data[1].append(
float(((numpy.int8(pol1_r_bits << 4) >> 4))) +
(1j * float(((numpy.int8(pol1_i_bits << 4) >> 4)))))
_log('returning %i complex values for each pol.' % len(data[0]))
return data
def get_snap_feng_10gbe(c, fpgas = [], offset = -1, man_trigger = False, man_valid = False):
if len(fpgas) == 0:
fpgas = c.ffpgas
corr_functions.write_masked_register(fpgas, register_fengine_control, debug_snap_select = snap_fengine_debug_select['gbetx0_128'])
snap_data = snap.snapshots_get(fpgas = fpgas, dev_names = snap_debug, wait_period = 3, offset = offset, man_trig = man_trigger, man_valid = man_valid, circular_capture = False)
rd = []
for ctr in range(0, len(snap_data['data'])):
d = snap_data['data'][ctr]
repeater = construct.GreedyRepeater(snap_fengine_gbe_tx)
up = repeater.parse(d)
for a in up:
a['link_down'] = not a['link_up']
a['hdr_valid'] = False
a['mrst'] = False
a['sync'] = False
rd.append(up)
return rd
def get_snap_ct(c, fpgas=[], offset=-1, setup_snap=True):
"""
Read and return data from the corner turner. Both pols are returned.
"""
if len(fpgas) == 0:
fpgas = c.ffpgas
if setup_snap:
corr_functions.write_masked_register(
fpgas,
register_fengine_control,
debug_snap_select=snap_fengine_debug_select['ct_64'])
snap_data = snap.snapshots_get(fpgas=fpgas,
dev_names=snap_debug,
wait_period=3,
offset=offset)
rd = []
for ctr in range(0, len(snap_data['data'])):
d = snap_data['data'][ctr]
repeater = construct.GreedyRepeater(snap_fengine_debug_ct)
up = repeater.parse(d)
fdata_p0 = []
fdata_p1 = []
for a in up:
p0 = []
p1 = []
p0.append(
bin2fp(a['p00_r'], 4, 3) + (1j * bin2fp(a['p00_i'], 4, 3)))
p0.append(
bin2fp(a['p01_r'], 4, 3) + (1j * bin2fp(a['p01_i'], 4, 3)))
p0.append(
bin2fp(a['p02_r'], 4, 3) + (1j * bin2fp(a['p02_i'], 4, 3)))
p0.append(
bin2fp(a['p03_r'], 4, 3) + (1j * bin2fp(a['p03_i'], 4, 3)))
p1.append(
bin2fp(a['p10_r'], 4, 3) + (1j * bin2fp(a['p10_i'], 4, 3)))
p1.append(
bin2fp(a['p11_r'], 4, 3) + (1j * bin2fp(a['p11_i'], 4, 3)))
p1.append(
bin2fp(a['p12_r'], 4, 3) + (1j * bin2fp(a['p12_i'], 4, 3)))
p1.append(
bin2fp(a['p13_r'], 4, 3) + (1j * bin2fp(a['p13_i'], 4, 3)))
fdata_p0.extend(p0)
fdata_p1.extend(p1)
rd.append([fdata_p0, fdata_p1])
return rd
def get_snap_adc_DUMB(c, fpgas = [], wait_period = 3):
"""
Read raw samples from the ADC snap block.
2 pols, each one 4 parallel samples f8.7. So 64-bits total.
"""
raw = snap.snapshots_get(fpgas = fpgas, dev_names = snap_adc, wait_period = wait_period)
repeater = construct.GreedyRepeater(snap_fengine_adc)
rv = []
for index, d in enumerate(raw['data']):
data = [[],[]]
od = numpy.fromstring(d, dtype = numpy.int8)
for ctr in range(0, len(od), 8):
for ctr2 in range(0,4):
data[0].append(od[ctr + ctr2])
for ctr2 in range(4,8):
data[1].append(od[ctr + ctr2])
data = [numpy.array(data[0], dtype=numpy.int8), numpy.array(data[1], dtype=numpy.int8)]
v = {'fpga_index': index, 'data': data}
rv.append(v)
return rv
def get_snap_fine_fft(c, fpgas = [], offset = -1, setup_snap = True):
if len(fpgas) == 0:
fpgas = c.ffpgas
if setup_snap:
corr_functions.write_masked_register(fpgas, register_fengine_control, debug_snap_select = snap_fengine_debug_select['fine_128'])
snap_data = snap.snapshots_get(fpgas = fpgas, dev_names = snap_debug, wait_period = 3, offset = offset)
rd = []
for ctr in range(0, len(snap_data['data'])):
d = snap_data['data'][ctr]
repeater = construct.GreedyRepeater(snap_fengine_debug_fine_fft)
up = repeater.parse(d)
fdata_p0 = []
fdata_p1 = []
for a in up:
p0c = bin2fp(a['p0_r'], fine_fft_bitwidth, 17) + (1j * bin2fp(a['p0_i'], fine_fft_bitwidth, 17))
p1c = bin2fp(a['p1_r'], fine_fft_bitwidth, 17) + (1j * bin2fp(a['p1_i'], fine_fft_bitwidth, 17))
fdata_p0.append(p0c)
fdata_p1.append(p1c)
rd.append([fdata_p0, fdata_p1])
return rd
def get_snap_adc(c, fpgas = [], wait_period = 3):
"""
Read raw samples from the ADC snap block.
2 pols, each one 4 parallel samples f8.7. So 64-bits total.
"""
raw = snap.snapshots_get(fpgas = fpgas, dev_names = snap_adc, wait_period = wait_period)
repeater = construct.GreedyRepeater(snap_fengine_adc)
rv = []
for index, d in enumerate(raw['data']):
upd = repeater.parse(d)
data = [[], []]
for ctr in range(0, len(upd)):
for pol in range(0,2):
for sample in range(0,4):
uf = upd[ctr]['d%i_%i' % (pol,sample)]
f87 = bin2fp(uf)
data[pol].append(f87)
v = {'fpga_index': index, 'data': data}
rv.append(v)
return rv
def _fpga_snap_quant(fpga = None, offset = -1, wbc_compat = False, debug_data = None):
''''
Get quantiser snap data from only one f-engine FPGA.
NB: Assumes the quantiser has already been selected in the control register.
Returns a snapshot of quantised data in one of two formats, depending on the wbc_compat argument.
Either way, it's data for both pols.
debug_data is data from the snap.snapshots_get function
'''
def _log(msg):
fpga._logger.debug('_fpga_snap_quant: %s' % msg)
if fpga == None:
raise RuntimeError('Please provide the FPGA from which to read the quantised data.')
if debug_data == None:
_log('reading snap data at offset %i.' % offset)
snap_data = snap.snapshots_get(fpgas = [fpga], dev_names = snap_debug, wait_period = 3, offset = offset)['data'][0]
else:
_log('using debug data, not fresh snap data.')
snap_data = debug_data['data'][0]
_log('unpacking data.')
data = [[], []]
if not wbc_compat:
repeater = construct.GreedyRepeater(snap_fengine_debug_quant)
unpacked = repeater.parse(snap_data)
for ctr in unpacked:
p0c = bin2fp(ctr['p0_r'], 4, 3) + (1j * bin2fp(ctr['p0_i'], 4, 3))
p1c = bin2fp(ctr['p1_r'], 4, 3) + (1j * bin2fp(ctr['p1_i'], 4, 3))
data[0].append(p0c)
data[1].append(p1c)
else:
# remember that the data is 16-bit padded up to 128-bit because of the one debug snap block, so only 2 of every 16 bytes are valid data
unpacked = numpy.fromstring(snap_data, dtype = numpy.uint8)
for ctr in range(14, len(unpacked), 16):
pol0_r_bits = (unpacked[ctr] & ((2**8) - (2**4))) >> 4
pol0_i_bits = (unpacked[ctr] & ((2**4) - (2**0)))
pol1_r_bits = (unpacked[ctr+1] & ((2**8) - (2**4))) >> 4
pol1_i_bits = (unpacked[ctr+1] & ((2**4) - (2**0)))
data[0].append(float(((numpy.int8(pol0_r_bits << 4) >> 4))) + (1j * float(((numpy.int8(pol0_i_bits << 4) >> 4)))))
data[1].append(float(((numpy.int8(pol1_r_bits << 4) >> 4))) + (1j * float(((numpy.int8(pol1_i_bits << 4) >> 4)))))
_log('returning %i complex values for each pol.' % len(data[0]))
return data
def get_snap_adc(c, fpgas=[], wait_period=3):
"""
Read raw samples from the ADC snap block.
2 pols, each one 4 parallel samples f8.7. So 64-bits total.
"""
raw = snap.snapshots_get(fpgas=fpgas,
dev_names=snap_adc,
wait_period=wait_period)
repeater = construct.GreedyRepeater(snap_fengine_adc)
rv = []
for index, d in enumerate(raw['data']):
upd = repeater.parse(d)
data = [[], []]
for ctr in range(0, len(upd)):
for pol in range(0, 2):
for sample in range(0, 4):
uf = upd[ctr]['d%i_%i' % (pol, sample)]
f87 = bin2fp(uf)
data[pol].append(f87)
v = {'fpga_index': index, 'data': data}
rv.append(v)
return rv
def get_snap_coarse_channel(c, fpgas=[], pol=0, channel=-1, setup_snap=True):
"""
Get data from a specific coarse channel - straight out of the FFT into the snap block, NOT via the buffer block.
Returns a list of the data from only that polarisation.
"""
if channel == -1:
raise RuntimeError('Cannot get data from unspecified channel.')
if len(fpgas) == 0:
fpgas = c.ffpgas
if setup_snap:
corr_functions.write_masked_register(
fpgas,
register_fengine_control,
debug_snap_select=snap_fengine_debug_select['coarse_72'])
corr_functions.write_masked_register(fpgas,
register_fengine_coarse_control,
debug_pol_select=pol,
debug_specify_chan=1,
debug_chan=channel >> 1)
snap_data = snap.snapshots_get(fpgas=fpgas,
dev_names=snap_debug,
wait_period=3)
rd = []
for ctr in range(0, len(snap_data['data'])):
d = snap_data['data'][ctr]
repeater = construct.GreedyRepeater(snap_fengine_debug_coarse_fft)
up = repeater.parse(d)
coarsed = []
for a in up:
if channel & 1:
num = bin2fp(a['d1_r'], 18,
17) + (1j * bin2fp(a['d1_i'], 18, 17))
else:
num = bin2fp(a['d0_r'], 18,
17) + (1j * bin2fp(a['d0_i'], 18, 17))
coarsed.append(num)
rd.append(coarsed)
return rd
def get_snap_coarse_fft(c, fpgas = [], pol = 0, setup_snap = True):
"""
Read and return data from the coarse FFT.
Returns a list of the data from only that polarisation.
"""
if len(fpgas) == 0:
fpgas = c.ffpgas
if setup_snap:
corr_functions.write_masked_register(fpgas, register_fengine_control, debug_snap_select = snap_fengine_debug_select['coarse_72'])
corr_functions.write_masked_register(fpgas, register_fengine_coarse_control, debug_pol_select = pol, debug_specify_chan = 0)
snap_data = snap.snapshots_get(fpgas = fpgas, dev_names = snap_debug, wait_period = 3)
rd = []
for ctr in range(0, len(snap_data['data'])):
d = snap_data['data'][ctr]
repeater = construct.GreedyRepeater(snap_fengine_debug_coarse_fft)
up = repeater.parse(d)
coarsed = []
for a in up:
for b in range(0,2):
num = bin2fp(a['d%i_r'%b], 18, 17) + (1j * bin2fp(a['d%i_i'%b], 18, 17))
coarsed.append(num)
rd.append(coarsed)
return rd
def get_snap_xaui(c,
fpgas=[],
offset=-1,
man_trigger=False,
man_valid=False,
wait_period=3):
"""
Read the XAUI data out of the general debug snap block.
"""
if len(fpgas) == 0:
fpgas = c.ffpgas
corr_functions.write_masked_register(
fpgas,
register_fengine_control,
debug_snap_select=snap_fengine_debug_select['xaui_128'])
snap_data = snap.snapshots_get(fpgas=fpgas,
dev_names=snap_debug,
wait_period=wait_period,
offset=offset,
man_trig=man_trigger,
man_valid=man_valid,
circular_capture=False)
return snap_data
def get_snap_buffer_pfb(c, fpgas = [], pol = 0, setup_snap = True, pfb = False):
'''This DOESN'T EXIST in regular F-engines. Only in specific debug versions.
'''
if len(fpgas) == 0:
fpgas = c.ffpgas
if setup_snap:
if pfb:
corr_functions.write_masked_register(fpgas, register_fengine_control, debug_snap_select = snap_fengine_debug_select['pfb_72'])
else:
corr_functions.write_masked_register(fpgas, register_fengine_control, debug_snap_select = snap_fengine_debug_select['buffer_72'])
corr_functions.write_masked_register(fpgas, register_fengine_coarse_control, debug_pol_select = pol)
snap_data = snap.snapshots_get(fpgas = fpgas, dev_names = snap_debug, wait_period = 3)
rd = []
for ctr in range(0, len(snap_data['data'])):
d = snap_data['data'][ctr]
repeater = construct.GreedyRepeater(snap_fengine_debug_coarse_fft)
up = repeater.parse(d)
coarsed = []
for a in up:
num = bin2fp(a['d%i_r'%pol], 18, 17) + (1j * bin2fp(a['d%i_i'%pol], 18, 17))
coarsed.append(num)
rd.append(coarsed)
return rd
def DONE_get_ct_snap(correlator, offset = -1):
corr_functions.write_masked_register(correlator.ffpgas, register_fengine_fine_control, quant_snap_select = 2)
raw = snap.snapshots_get(correlator.ffpgas, dev_names = fine_snap_name, man_trig = False, man_valid = False, wait_period = 3, offset = offset, circular_capture = False)
chan_values = []
for index, d in enumerate(raw['data']):
up = list(struct.unpack('>%iI' % (len(d) / 4), d))
values = [[], []]
for value in up:
# two freq channel values for the same freq-channel, both pols
# will have to use the offset to get multiple freq channels
p00 = value >> 24
p10 = (value >> 16) & 0xff
p01 = (value >> 8) & 0xff
p11 = value & 0xff
def extract8bit(v8):
r = (v8 & ((2**8) - (2**4))) >> 4
i = (v8 & ((2**4) - (2**0)))
return r + (1j * i)
values[0].append(value >> 24)
values[0].append((value >> 8) & 0xff)
values[1].append((value >> 16) & 0xff)
values[1].append(value & 0xff)
chan_values.append({'fpga_index': index, 'data': values})
return chan_values
