def set_register():
"""
For DVT/EVT boards the framework is not able to handle for GPIOI4 and
causes error : 'Failed to configure "GPIOI4" for "BMC_SPI1_CS0":
Not able to unsatisfy an AND condition'. In order to fix the error
set the specific bit in the register so the framework can handle it.
"""
"""
The write operation to SCU70 only can set to ’1’,
to clear to ’0’, it must write ’1’ to SCU7C (write 1 clear).
"""
l_reg = soc_get_register(0x7C)
l_reg.set_bit(5, write_through=True)
l_reg = soc_get_register(0x7C)
l_reg.set_bit(12, write_through=True)
def set_register():
'''
For DVT/EVT boards the framework is not able to handle for GPIOS0 and
causes error : 'Failed to configure "GPIOS0" for "BMC_SPI_WP_N":
Not able to unsatisfy an AND condition'. In order to fix the error
set the specific bit in the register so the framework can handle it.
'''
l_reg = soc_get_register(0x8C)
l_reg.clear_bit(0, write_through=True)
def set_register():
'''
For DVT/EVT boards the framework is not able to handle for GPIOS0 and
causes error : 'Failed to configure "GPIOS0" for "BMC_SPI_WP_N":
Not able to unsatisfy an AND condition'. In order to fix the error
set the specific bit in the register so the framework can handle it.
'''
l_reg = soc_get_register(0x8C)
l_reg.clear_bit(0, write_through=True)
def satisfy(self, **kwargs):
if BitsEqual.check(self):
return
reg = soc_get_register(self.register)
value = self.value
for bit in sorted(self.bits):
if value & 0x1 == 0x1:
reg.set_bit(bit, **kwargs)
else:
reg.clear_bit(bit, **kwargs)
value >>= 1
def satisfy(self, **kwargs):
if BitsEqual.check(self):
return
reg = soc_get_register(self.register)
value = self.value
for bit in sorted(self.bits):
if value & 0x1 == 0x1:
reg.set_bit(bit, **kwargs)
else:
reg.clear_bit(bit, **kwargs)
value >>= 1
def unsatisfy(self, **kwargs):
if not BitsEqual.check(self):
return
if len(self.bits) > 1:
raise NotSmartEnoughException('Not able to unsatisfy '
'multi-bits equal')
bit = self.bits[0]
reg = soc_get_register(self.register)
value = self.value
if value & 0x1 == 0x1:
reg.clear_bit(bit, **kwargs)
else:
reg.set_bit(bit, **kwargs)
def unsatisfy(self, **kwargs):
if not BitsEqual.check(self):
return
if len(self.bits) > 1:
raise NotSmartEnoughException('Not able to unsatisfy '
'multi-bits equal')
bit = self.bits[0]
reg = soc_get_register(self.register)
value = self.value
if value & 0x1 == 0x1:
reg.clear_bit(bit, **kwargs)
else:
reg.set_bit(bit, **kwargs)
def __str__(self):
return '%s[%s]!=0x%x' \
% (str(soc_get_register(self.register)), self.bits, self.value)
def check(self):
return soc_get_register(self.register).bits_value(self.bits) \
== self.value
def write_to_hw(self):
for reg in self.registers:
soc_get_register(reg).write()
def _sync_from_hw(self):
# for each register, create an object and read the value from HW
for reg in self.registers:
soc_get_register(reg).read(refresh=True)
def __str__(self):
return '%s[%s]!=0x%x' \
% (str(soc_get_register(self.register)), self.bits, self.value)
def check(self):
return soc_get_register(self.register).bits_value(self.bits) \
== self.value
def write_to_hw(self):
for reg in self.registers:
soc_get_register(reg).write()
def _sync_from_hw(self):
# for each register, create an object and read the value from HW
for reg in self.registers:
soc_get_register(reg).read(refresh=True)
def __str__(self):
return "%s[%s]==0x%x" % (
str(soc_get_register(self.register)),
self.bits,
self.value,
)
