def test_partition_with_more_sdram_than_default(self):
"""
test that the partitioner works when its machine is slightly malformed
in that it has more SDRAM available
"""
n_processors = 18
(e, ne, n, w, _, _) = range(6)
links = list()
links.append(Link(0, 0, e, 0, 1))
_sdram = SDRAM(128 * (2**21))
links = list()
links.append(Link(0, 0, e, 1, 1))
links.append(Link(0, 1, ne, 1, 0))
links.append(Link(1, 1, n, 0, 0))
links.append(Link(1, 0, w, 0, 1))
r = Router(links, False, 1024)
ip = "192.162.240.253"
chips = list()
for x in range(5):
for y in range(5):
if x == y == 0:
chips.append(Chip(x, y, n_processors, r, _sdram, 0, 0, ip))
else:
chips.append(Chip(x, y, n_processors, r, _sdram, 0, 0))
self.machine = machine_from_chips(chips)
splitter_partitioner(self.graph, self.machine, 3000,
PreAllocatedResourceContainer())
def test_partition_with_more_sdram_than_default(self):
"""
test that the partitioner works when its machine is slightly malformed
in that it has more sdram avilable
"""
self.setup()
flops = 20000000
(e, _, n, w, _, s) = range(6)
processors = list()
for i in range(18):
processors.append(Processor(i, flops))
links = list()
links.append(Link(0, 0, 0, 0, 1, s, s))
_sdram = SDRAM(128 * (2**21))
links = list()
links.append(Link(0, 0, 0, 1, 1, n, n))
links.append(Link(0, 1, 1, 1, 0, s, s))
links.append(Link(1, 1, 2, 0, 0, e, e))
links.append(Link(1, 0, 3, 0, 1, w, w))
r = Router(links, False, 100, 1024)
ip = TestBasicPartitioner.TheTestAddress
chips = list()
for x in range(5):
for y in range(5):
chips.append(Chip(x, y, processors, r, _sdram, 0, 0, ip))
self.machine = Machine(chips, 0, 0)
self.bp(self.graph, self.machine)
def test_partition_with_more_sdram_than_default(self):
"""
test that the partitioner works when its machine is slightly malformed
in that it has more SDRAM available
"""
self.setup()
n_processors = 18
(e, ne, n, w, _, _) = range(6)
links = list()
links.append(Link(0, 0, e, 0, 1))
_sdram = SDRAM(128 * (2**21))
links = list()
links.append(Link(0, 0, e, 1, 1))
links.append(Link(0, 1, ne, 1, 0))
links.append(Link(1, 1, n, 0, 0))
links.append(Link(1, 0, w, 0, 1))
r = Router(links, False, 1024)
ip = TestBasicPartitioner.TheTestAddress
chips = list()
for x in range(5):
for y in range(5):
if x == y == 0:
chips.append(Chip(x, y, n_processors, r, _sdram, 0, 0, ip))
else:
chips.append(Chip(x, y, n_processors, r, _sdram, 0, 0))
self.machine = machine_from_chips(chips)
self.sp(self.graph, self.machine, 3000)
def test_with_application_vertices(self):
""" Test that an application vertex's data is rewritten correctly
"""
# Create a default SDRAM to set the max to default
SDRAM()
reload_region_data = [(0, [0] * 10), (1, [1] * 20)]
vertex = _TestApplicationVertex(10, reload_region_data)
m_slice_1 = Slice(0, 4)
m_slice_2 = Slice(5, 9)
m_vertex_1 = vertex.create_machine_vertex(m_slice_1, None, None, None)
m_vertex_2 = vertex.create_machine_vertex(m_slice_2, None, None, None)
graph_mapper = GraphMapper()
graph_mapper.add_vertex_mapping(m_vertex_1, m_slice_1, vertex)
graph_mapper.add_vertex_mapping(m_vertex_2, m_slice_2, vertex)
placements = Placements(
[Placement(m_vertex_1, 0, 0, 1),
Placement(m_vertex_2, 0, 0, 2)])
user_0_addresses = {
(placement.x, placement.y, placement.p): i * 1000
for i, placement in enumerate(placements.placements)
}
region_addresses = [i for i in range(MAX_MEM_REGIONS)]
transceiver = _MockTransceiver(user_0_addresses, region_addresses)
reloader = DSGRegionReloader()
reloader.__call__(transceiver, placements, "localhost", "test", False,
"test", graph_mapper)
regions_rewritten = transceiver.regions_rewritten
# Check that the number of times the data has been regenerated is
# correct
self.assertEqual(vertex.regenerate_call_count, placements.n_placements)
# Check that the number of regions rewritten is correct
self.assertEqual(len(transceiver.regions_rewritten),
placements.n_placements * len(reload_region_data))
# Check that the data rewritten is correct
for i, placement in enumerate(placements.placements):
user_0_address = user_0_addresses[placement.x, placement.y,
placement.p]
for j in range(len(reload_region_data)):
pos = (i * len(reload_region_data)) + j
region, data = reload_region_data[j]
address = get_region_base_address_offset(
user_0_address, 0) + region_addresses[region]
data = bytearray(numpy.array(data, dtype="uint32").tobytes())
# Check that the base address and data written is correct
self.assertEqual(regions_rewritten[pos], (address, data))
# Delete data files
shutil.rmtree("test")
def create_virtual_chip(machine, link_data, virtual_chip_x, virtual_chip_y):
# If the chip already exists, return the data
if machine.is_chip_at(virtual_chip_x, virtual_chip_y):
if not machine.get_chip_at(virtual_chip_x, virtual_chip_y).virtual:
raise Exception(
"Attempting to add virtual chip in place of a real chip")
return
# Create link to the virtual chip from the real chip
virtual_link_id = (link_data.connected_link + 3) % 6
to_virtual_chip_link = Link(
destination_x=virtual_chip_x,
destination_y=virtual_chip_y,
source_x=link_data.connected_chip_x,
source_y=link_data.connected_chip_y,
multicast_default_from=virtual_link_id,
multicast_default_to=virtual_link_id,
source_link_id=link_data.connected_link)
# Create link to the real chip from the virtual chip
from_virtual_chip_link = Link(
destination_x=link_data.connected_chip_x,
destination_y=link_data.connected_chip_y,
source_x=virtual_chip_x,
source_y=virtual_chip_y,
multicast_default_from=link_data.connected_link,
multicast_default_to=link_data.connected_link,
source_link_id=virtual_link_id)
# create the router
links = [from_virtual_chip_link]
router_object = Router(
links=links, emergency_routing_enabled=False,
clock_speed=Router.ROUTER_DEFAULT_CLOCK_SPEED,
n_available_multicast_entries=sys.maxsize)
# create the processors
processors = list()
for virtual_core_id in range(0, constants.CORES_PER_VIRTUAL_CHIP):
processors.append(Processor.factory(virtual_core_id))
# connect the real chip with the virtual one
connected_chip = machine.get_chip_at(
link_data.connected_chip_x,
link_data.connected_chip_y)
connected_chip.router.add_link(to_virtual_chip_link)
machine.add_chip(Chip(
processors=processors, router=router_object,
sdram=SDRAM(size=0),
x=virtual_chip_x, y=virtual_chip_y,
virtual=True, nearest_ethernet_x=None, nearest_ethernet_y=None))
def setUp(self):
"""
setup for all basic partitioner tests
"""
unittest_setup()
self.vert1 = SimpleTestVertex(10, "New AbstractConstrainedVertex 1")
self.vert1.splitter = SplitterSliceLegacy()
self.vert2 = SimpleTestVertex(5, "New AbstractConstrainedVertex 2")
self.vert2.splitter = SplitterSliceLegacy()
self.vert3 = SimpleTestVertex(3, "New AbstractConstrainedVertex 3")
self.vert3.splitter = SplitterSliceLegacy()
self.edge1 = ApplicationEdge(self.vert1,
self.vert2,
label="First edge")
self.edge2 = ApplicationEdge(self.vert2,
self.vert1,
label="Second edge")
self.edge3 = ApplicationEdge(self.vert1,
self.vert3,
label="Third edge")
self.verts = [self.vert1, self.vert2, self.vert3]
self.edges = [self.edge1, self.edge2, self.edge3]
self.graph = ApplicationGraph("Graph")
self.graph.add_vertices(self.verts)
self.graph.add_edges(self.edges, "foo")
n_processors = 18
(e, ne, n, w, _, _) = range(6)
links = list()
links.append(Link(0, 0, e, 0, 1))
_sdram = SDRAM(128 * (2**20))
links = list()
links.append(Link(0, 0, e, 1, 1))
links.append(Link(0, 1, ne, 1, 0))
links.append(Link(1, 1, n, 0, 0))
links.append(Link(1, 0, w, 0, 1))
r = Router(links, False, 1024)
ip = TestBasicPartitioner.TheTestAddress
chips = list()
for x in range(5):
for y in range(5):
if x == y == 0:
chips.append(Chip(x, y, n_processors, r, _sdram, 0, 0, ip))
else:
chips.append(Chip(x, y, n_processors, r, _sdram, 0, 0))
self.machine = machine_from_chips(chips)
def create_virtual_chip(machine, link_data, virtual_chip_x, virtual_chip_y):
""" Create a virtual chip on a real machine.
:param ~spinn_machine.Machine machine:
:param ~spinn_machine.link_data_objects.AbstractLinkData link_data:
Describes the link from the real machine.
:param int virtual_chip_x: Virtual chip coordinate
:param int virtual_chip_y: Virtual chip coordinate
"""
# If the chip already exists, return the data
if machine.is_chip_at(virtual_chip_x, virtual_chip_y):
if not machine.get_chip_at(virtual_chip_x, virtual_chip_y).virtual:
raise Exception(
"Attempting to add virtual chip in place of a real chip")
return
# Create link to the virtual chip from the real chip
virtual_link_id = (link_data.connected_link + 3) % 6
to_virtual_chip_link = Link(destination_x=virtual_chip_x,
destination_y=virtual_chip_y,
source_x=link_data.connected_chip_x,
source_y=link_data.connected_chip_y,
source_link_id=link_data.connected_link)
# Create link to the real chip from the virtual chip
from_virtual_chip_link = Link(destination_x=link_data.connected_chip_x,
destination_y=link_data.connected_chip_y,
source_x=virtual_chip_x,
source_y=virtual_chip_y,
source_link_id=virtual_link_id)
# create the router
links = [from_virtual_chip_link]
router_object = Router(links=links,
emergency_routing_enabled=False,
n_available_multicast_entries=sys.maxsize)
# connect the real chip with the virtual one
connected_chip = machine.get_chip_at(link_data.connected_chip_x,
link_data.connected_chip_y)
connected_chip.router.add_link(to_virtual_chip_link)
machine.add_virtual_chip(
Chip(n_processors=constants.CORES_PER_VIRTUAL_CHIP,
router=router_object,
sdram=SDRAM(size=0),
x=virtual_chip_x,
y=virtual_chip_y,
virtual=True,
nearest_ethernet_x=None,
nearest_ethernet_y=None))
def test_overwrite(self):
# Create a sdram just to set max chip size
SDRAM(1000)
temp_spec = mktemp()
spec = DataSpecificationGenerator(io.FileIO(temp_spec, "w"))
spec.reserve_memory_region(0, 4)
spec.switch_write_focus(0)
spec.write_value(1)
spec.write_value(2)
spec.end_specification()
executor = DataSpecificationExecutor(io.FileIO(temp_spec, "r"), 400)
self.assertRaises(NoMoreException, executor.execute)
def setup(self):
"""
setup for all basic partitioner tests
"""
self.vert1 = SimpleTestVertex(10, "New AbstractConstrainedVertex 1")
self.vert2 = SimpleTestVertex(5, "New AbstractConstrainedVertex 2")
self.vert3 = SimpleTestVertex(3, "New AbstractConstrainedVertex 3")
self.edge1 = ApplicationEdge(self.vert1, self.vert2, None,
"First edge")
self.edge2 = ApplicationEdge(self.vert2, self.vert1, None,
"Second edge")
self.edge3 = ApplicationEdge(self.vert1, self.vert3, None,
"Third edge")
self.verts = [self.vert1, self.vert2, self.vert3]
self.edges = [self.edge1, self.edge2, self.edge3]
self.graph = ApplicationGraph("Graph")
self.graph.add_vertices(self.verts)
self.graph.add_edges(self.edges, "foo")
flops = 200000000
(e, _, n, w, _, s) = range(6)
processors = list()
for i in range(18):
processors.append(Processor(i, flops))
links = list()
links.append(Link(0, 0, 0, 0, 1, s, s))
_sdram = SDRAM(128 * (2**20))
links = list()
links.append(Link(0, 0, 0, 1, 1, n, n))
links.append(Link(0, 1, 1, 1, 0, s, s))
links.append(Link(1, 1, 2, 0, 0, e, e))
links.append(Link(1, 0, 3, 0, 1, w, w))
r = Router(links, False, 100, 1024)
ip = TestBasicPartitioner.TheTestAddress
chips = list()
for x in range(5):
for y in range(5):
chips.append(Chip(x, y, processors, r, _sdram, 0, 0, ip))
self.machine = Machine(chips, 0, 0)
self.bp = BasicPartitioner()
def test_complex_spec(self):
# Create a sdram just to set max chip size
SDRAM(1000)
temp_spec = mktemp()
spec = DataSpecificationGenerator(io.FileIO(temp_spec, "w"))
spec.reserve_memory_region(0, 44)
spec.switch_write_focus(0)
spec.set_register_value(3, 0x31323341)
spec.write_value_from_register(3)
spec.set_register_value(3, 0x31323342)
spec.write_value_from_register(3)
spec.set_register_value(3, 0x31323344)
spec.write_value_from_register(3)
spec.set_register_value(3, 0x31323347)
spec.write_value_from_register(3)
spec.set_register_value(3, 0x3132334B)
spec.write_value_from_register(3)
spec.set_register_value(2, 24)
spec.set_write_pointer(2, address_is_register=True)
spec.write_array([0x61, 0x62, 0x63, 0x64], data_type=DataType.UINT8)
spec.set_register_value(5, 4)
spec.write_repeated_value(0x70,
5,
repeats_is_register=True,
data_type=DataType.UINT8)
spec.write_value(0x7d, data_type=DataType.INT64)
spec.end_specification()
executor = DataSpecificationExecutor(io.FileIO(temp_spec, "r"), 400)
executor.execute()
r = executor.get_region(0)
self.assertEqual(r.allocated_size, 44)
self.assertEqual(r.max_write_pointer, 40)
self.assertFalse(r.unfilled)
self.assertEqual(
r.region_data,
bytearray("A321"
"B321"
"D321"
"G321"
"K321"
"\0\0\0\0"
"abcd"
"pppp"
"}\0\0\0"
"\0\0\0\0"
"\0\0\0\0".encode("ISO 8859-1")))
def test_partition_with_barely_sufficient_space(self):
"""
test that partitioning will work when close to filling the machine
"""
self.setup()
n_processors = 18
(e, ne, n, w, _, _) = range(6)
links = list()
links.append(Link(0, 0, e, 0, 1))
_sdram = SDRAM(2**12)
links = list()
links.append(Link(0, 0, e, 1, 1))
links.append(Link(0, 1, ne, 1, 0))
links.append(Link(1, 1, n, 0, 0))
links.append(Link(1, 0, w, 0, 1))
r = Router(links, False, 1024)
ip = "192.162.240.253"
chips = list()
for x in range(5):
for y in range(5):
if x == y == 0:
chips.append(Chip(x, y, n_processors, r, _sdram, 0, 0, ip))
else:
chips.append(Chip(x, y, n_processors, r, _sdram, 0, 0))
self.machine = machine_from_chips(chips)
n_neurons = 17 * 5 * 5
singular_vertex = SimpleTestVertex(n_neurons,
"Large vertex",
max_atoms_per_core=1)
singular_vertex.splitter = SplitterSliceLegacy()
self.assertEqual(singular_vertex._model_based_max_atoms_per_core, 1)
self.graph = ApplicationGraph("Graph with large vertex")
self.graph.add_vertex(singular_vertex)
graph, _ = self.bp(
self.graph,
self.machine,
plan_n_time_steps=100,
pre_allocated_resources=PreAllocatedResourceContainer())
self.assertEqual(singular_vertex._model_based_max_atoms_per_core, 1)
self.assertEqual(len(list(graph.vertices)), n_neurons)
def test_allocate_resources_when_chip_used(self):
router = Router([])
sdram = SDRAM()
empty_chip = Chip(0,
0,
1,
router,
sdram,
0,
0,
"127.0.0.1",
virtual=False,
tag_ids=[1])
machine = machine_from_chips([empty_chip])
resource_tracker = ResourceTracker(machine, plan_n_timesteps=None)
with self.assertRaises(PacmanValueError):
resource_tracker.allocate_resources(
ResourceContainer(sdram=ConstantSDRAM(1024)))
def _make_chip(self, chip_info, machine):
""" Creates a chip from a ChipSummaryInfo structure.
:param ChipSummaryInfo chip_info:
The ChipSummaryInfo structure to create the chip from
:return: The created chip
:rtype: ~spinn_machine.Chip
"""
# Create the down cores set if any
n_cores = min(chip_info.n_cores, Machine.max_cores_per_chip())
core_states = chip_info.core_states
down_cores = self._ignore_cores_map.get((chip_info.x, chip_info.y),
None)
for i in range(1, n_cores):
if core_states[i] != CPUState.IDLE:
self._report_ignore("Not using core {}, {}, {} in state {}",
chip_info.x, chip_info.y, i,
core_states[i])
if down_cores is None:
down_cores = set()
down_cores.add(i)
# Create the router
router = self._make_router(chip_info, machine)
# Create the chip's SDRAM object
sdram_size = chip_info.largest_free_sdram_block
max_sdram_size = get_config_int("Machine",
"max_sdram_allowed_per_chip")
if (max_sdram_size is not None and sdram_size > max_sdram_size):
sdram_size = max_sdram_size
sdram = SDRAM(size=sdram_size)
# Create the chip
return Chip(x=chip_info.x,
y=chip_info.y,
n_processors=n_cores,
router=router,
sdram=sdram,
ip_address=chip_info.ethernet_ip_address,
nearest_ethernet_x=chip_info.nearest_ethernet_x,
nearest_ethernet_y=chip_info.nearest_ethernet_y,
down_cores=down_cores,
parent_link=chip_info.parent_link)
def test_partition_with_insufficient_space(self):
"""
test that if there's not enough space, the test the partitioner will
raise an error
"""
self.setup()
n_processors = 18
(e, ne, n, w, _, _) = range(6)
links = list()
links.append(Link(0, 0, e, 0, 1))
_sdram = SDRAM(2**11)
links = list()
links.append(Link(0, 0, e, 1, 1))
links.append(Link(0, 1, ne, 1, 0))
links.append(Link(1, 1, n, 0, 0))
links.append(Link(1, 0, w, 0, 1))
r = Router(links, False, 1024)
ip = "192.162.240.253"
chips = list()
for x in range(5):
for y in range(5):
if x == y == 0:
chips.append(Chip(x, y, n_processors, r, _sdram, 0, 0, ip))
else:
chips.append(Chip(x, y, n_processors, r, _sdram, 0, 0))
self.machine = machine_from_chips(chips)
large_vertex = SimpleTestVertex(3000,
"Large vertex",
max_atoms_per_core=1)
large_vertex.splitter = SplitterSliceLegacy()
self.assertEqual(large_vertex._model_based_max_atoms_per_core, 1)
self.graph = ApplicationGraph("Graph with large vertex")
self.graph.add_vertex(large_vertex)
with self.assertRaises(PacmanValueError):
self.bp(self.graph, self.machine, 3000,
PreAllocatedResourceContainer())
def test_partition_with_barely_sufficient_space(self):
"""
test that partitioning will work when close to filling the machine
"""
self.setup()
flops = 20000000
(e, _, n, w, _, s) = range(6)
processors = list()
for i in range(18):
processors.append(Processor(i, flops))
links = list()
links.append(Link(0, 0, 0, 0, 1, s, s))
_sdram = SDRAM(2**12)
links = list()
links.append(Link(0, 0, 0, 1, 1, n, n))
links.append(Link(0, 1, 1, 1, 0, s, s))
links.append(Link(1, 1, 2, 0, 0, e, e))
links.append(Link(1, 0, 3, 0, 1, w, w))
r = Router(links, False, 100, 1024)
ip = TestBasicPartitioner.TheTestAddress
chips = list()
for x in range(5):
for y in range(5):
chips.append(Chip(x, y, processors, r, _sdram, 0, 0, ip))
self.machine = Machine(chips, 0, 0)
singular_vertex = SimpleTestVertex(450,
"Large vertex",
max_atoms_per_core=1)
self.assertEqual(singular_vertex._model_based_max_atoms_per_core, 1)
self.graph = ApplicationGraph("Graph with large vertex")
self.graph.add_vertex(singular_vertex)
graph, _, _ = self.bp(self.graph, self.machine)
self.assertEqual(singular_vertex._model_based_max_atoms_per_core, 1)
self.assertEqual(len(list(graph.vertices)), 450)
def test_partition_with_insufficient_space(self):
"""
test that if there's not enough space, the test the partitioner will
raise an error
"""
self.setup()
flops = 1000
(e, _, n, w, _, s) = range(6)
processors = list()
for i in range(18):
processors.append(Processor(i, flops))
links = list()
links.append(Link(0, 0, 0, 0, 1, s, s))
_sdram = SDRAM(2**11)
links = list()
links.append(Link(0, 0, 0, 1, 1, n, n))
links.append(Link(0, 1, 1, 1, 0, s, s))
links.append(Link(1, 1, 2, 0, 0, e, e))
links.append(Link(1, 0, 3, 0, 1, w, w))
r = Router(links, False, 100, 1024)
ip = TestBasicPartitioner.TheTestAddress
chips = list()
for x in range(5):
for y in range(5):
chips.append(Chip(x, y, processors, r, _sdram, 0, 0, ip))
self.machine = Machine(chips, 0, 0)
large_vertex = SimpleTestVertex(3000,
"Large vertex",
max_atoms_per_core=1)
self.assertEqual(large_vertex._model_based_max_atoms_per_core, 1)
self.graph = ApplicationGraph("Graph with large vertex")
self.graph.add_vertex(large_vertex)
with self.assertRaises(PacmanPartitionException):
self.bp(self.graph, self.machine)
def test_write_synaptic_matrix_and_master_population_table(self):
MockSimulator.setup()
# Add an sdram so max SDRAM is high enough
SDRAM(10000)
# UGLY but the mock transceiver NEED generate_on_machine to be False
AbstractGenerateConnectorOnMachine.generate_on_machine = self.say_false
default_config_paths = os.path.join(
os.path.dirname(abstract_spinnaker_common.__file__),
AbstractSpiNNakerCommon.CONFIG_FILE_NAME)
config = conf_loader.load_config(
AbstractSpiNNakerCommon.CONFIG_FILE_NAME, default_config_paths)
config.set("Simulation", "one_to_one_connection_dtcm_max_bytes", 40)
machine_time_step = 1000.0
pre_app_vertex = SimpleApplicationVertex(10)
pre_vertex = SimpleMachineVertex(resources=None)
pre_vertex_slice = Slice(0, 9)
post_app_vertex = SimpleApplicationVertex(10)
post_vertex = SimpleMachineVertex(resources=None)
post_vertex_slice = Slice(0, 9)
post_slice_index = 0
one_to_one_connector_1 = OneToOneConnector(None)
direct_synapse_information_1 = SynapseInformation(
one_to_one_connector_1, pre_app_vertex, post_app_vertex, False,
False, None, SynapseDynamicsStatic(), 0, 1.5, 1.0)
one_to_one_connector_1.set_projection_information(
machine_time_step, direct_synapse_information_1)
one_to_one_connector_2 = OneToOneConnector(None)
direct_synapse_information_2 = SynapseInformation(
one_to_one_connector_2, pre_app_vertex, post_app_vertex, False,
False, None, SynapseDynamicsStatic(), 1, 2.5, 2.0)
one_to_one_connector_2.set_projection_information(
machine_time_step, direct_synapse_information_2)
all_to_all_connector = AllToAllConnector(None)
all_to_all_synapse_information = SynapseInformation(
all_to_all_connector, pre_app_vertex, post_app_vertex, False,
False, None, SynapseDynamicsStatic(), 0, 4.5, 4.0)
all_to_all_connector.set_projection_information(
machine_time_step, all_to_all_synapse_information)
app_edge = ProjectionApplicationEdge(
pre_app_vertex, post_app_vertex, direct_synapse_information_1)
app_edge.add_synapse_information(direct_synapse_information_2)
app_edge.add_synapse_information(all_to_all_synapse_information)
machine_edge = ProjectionMachineEdge(
app_edge.synapse_information, pre_vertex, post_vertex)
partition_name = "TestPartition"
graph = MachineGraph("Test")
graph.add_vertex(pre_vertex)
graph.add_vertex(post_vertex)
graph.add_edge(machine_edge, partition_name)
graph_mapper = GraphMapper()
graph_mapper.add_vertex_mapping(
pre_vertex, pre_vertex_slice, pre_app_vertex)
graph_mapper.add_vertex_mapping(
post_vertex, post_vertex_slice, post_app_vertex)
graph_mapper.add_edge_mapping(machine_edge, app_edge)
weight_scales = [4096.0, 4096.0]
key = 0
routing_info = RoutingInfo()
routing_info.add_partition_info(PartitionRoutingInfo(
[BaseKeyAndMask(key, 0xFFFFFFF0)],
graph.get_outgoing_edge_partition_starting_at_vertex(
pre_vertex, partition_name)))
temp_spec = tempfile.mktemp()
spec_writer = FileDataWriter(temp_spec)
spec = DataSpecificationGenerator(spec_writer, None)
master_pop_sz = 1000
master_pop_region = 0
all_syn_block_sz = 2000
synapse_region = 1
direct_region = 2
spec.reserve_memory_region(master_pop_region, master_pop_sz)
spec.reserve_memory_region(synapse_region, all_syn_block_sz)
synaptic_manager = SynapticManager(
n_synapse_types=2, ring_buffer_sigma=5.0,
spikes_per_second=100.0, config=config)
synaptic_manager._write_synaptic_matrix_and_master_population_table(
spec, [post_vertex_slice], post_slice_index, post_vertex,
post_vertex_slice, all_syn_block_sz, weight_scales,
master_pop_region, synapse_region, direct_region, routing_info,
graph_mapper, graph, machine_time_step)
spec.end_specification()
spec_writer.close()
spec_reader = FileDataReader(temp_spec)
executor = DataSpecificationExecutor(
spec_reader, master_pop_sz + all_syn_block_sz)
executor.execute()
master_pop_table = executor.get_region(0)
synaptic_matrix = executor.get_region(1)
direct_matrix = executor.get_region(2)
all_data = bytearray()
all_data.extend(master_pop_table.region_data[
:master_pop_table.max_write_pointer])
all_data.extend(synaptic_matrix.region_data[
:synaptic_matrix.max_write_pointer])
all_data.extend(direct_matrix.region_data[
:direct_matrix.max_write_pointer])
master_pop_table_address = 0
synaptic_matrix_address = master_pop_table.max_write_pointer
direct_synapses_address = (
synaptic_matrix_address + synaptic_matrix.max_write_pointer)
direct_synapses_address += 4
indirect_synapses_address = synaptic_matrix_address
placement = Placement(None, 0, 0, 1)
transceiver = MockTransceiverRawData(all_data)
# Get the master population table details
items = synaptic_manager._extract_synaptic_matrix_data_location(
key, master_pop_table_address, transceiver, placement)
# The first entry should be direct, but the rest should be indirect;
# the second is potentially direct, but has been restricted by the
# restriction on the size of the direct matrix
assert len(items) == 3
assert items[0][2]
assert not items[1][2]
assert not items[2][2]
data_1, row_len_1 = synaptic_manager._retrieve_synaptic_block(
txrx=transceiver, placement=placement,
master_pop_table_address=master_pop_table_address,
indirect_synapses_address=indirect_synapses_address,
direct_synapses_address=direct_synapses_address, key=key,
n_rows=pre_vertex_slice.n_atoms, index=0,
using_monitors=False)
connections_1 = synaptic_manager._read_synapses(
direct_synapse_information_1, pre_vertex_slice, post_vertex_slice,
row_len_1, 0, 2, weight_scales, data_1, None, machine_time_step)
# The first matrix is a 1-1 matrix, so row length is 1
assert row_len_1 == 1
# Check that all the connections have the right weight and delay
assert len(connections_1) == post_vertex_slice.n_atoms
assert all([conn["weight"] == 1.5 for conn in connections_1])
assert all([conn["delay"] == 1.0 for conn in connections_1])
data_2, row_len_2 = synaptic_manager._retrieve_synaptic_block(
txrx=transceiver, placement=placement,
master_pop_table_address=master_pop_table_address,
indirect_synapses_address=indirect_synapses_address,
direct_synapses_address=direct_synapses_address, key=key,
n_rows=pre_vertex_slice.n_atoms, index=1,
using_monitors=False)
connections_2 = synaptic_manager._read_synapses(
direct_synapse_information_2, pre_vertex_slice, post_vertex_slice,
row_len_2, 0, 2, weight_scales, data_2, None, machine_time_step)
# The second matrix is a 1-1 matrix, so row length is 1
assert row_len_2 == 1
# Check that all the connections have the right weight and delay
assert len(connections_2) == post_vertex_slice.n_atoms
assert all([conn["weight"] == 2.5 for conn in connections_2])
assert all([conn["delay"] == 2.0 for conn in connections_2])
data_3, row_len_3 = synaptic_manager._retrieve_synaptic_block(
txrx=transceiver, placement=placement,
master_pop_table_address=master_pop_table_address,
indirect_synapses_address=indirect_synapses_address,
direct_synapses_address=direct_synapses_address, key=key,
n_rows=pre_vertex_slice.n_atoms, index=2,
using_monitors=False)
connections_3 = synaptic_manager._read_synapses(
all_to_all_synapse_information, pre_vertex_slice,
post_vertex_slice, row_len_3, 0, 2, weight_scales, data_3, None,
machine_time_step)
# The third matrix is an all-to-all matrix, so length is n_atoms
assert row_len_3 == post_vertex_slice.n_atoms
# Check that all the connections have the right weight and delay
assert len(connections_3) == \
post_vertex_slice.n_atoms * pre_vertex_slice.n_atoms
assert all([conn["weight"] == 4.5 for conn in connections_3])
assert all([conn["delay"] == 4.0 for conn in connections_3])
def setUp(self):
#######################################################################
# Setting up vertices, edges and graph #
#######################################################################
self.vert1 = T_AppVertex(100, "New AbstractConstrainedVertex 1")
self.vert2 = T_AppVertex(5, "New AbstractConstrainedVertex 2")
self.vert3 = T_AppVertex(3, "New AbstractConstrainedVertex 3")
self.edge1 = ApplicationEdge(self.vert1, self.vert2, "First edge")
self.edge2 = ApplicationEdge(self.vert2, self.vert1, "Second edge")
self.edge3 = ApplicationEdge(self.vert1, self.vert3, "Third edge")
self.verts = [self.vert1, self.vert2, self.vert3]
self.edges = [self.edge1, self.edge2, self.edge3]
self.graph = ApplicationGraph("Graph", self.verts, self.edges)
#######################################################################
# Setting up machine #
#######################################################################
flops = 1000
(_, _, n, _, _, s) = range(6)
processors = list()
for i in range(18):
processors.append(Processor(i, flops))
_sdram = SDRAM(128 * (2**20))
ip = "192.168.240.253"
chips = list()
for x in range(10):
for y in range(10):
links = list()
links.append(Link(x, y, 0, (x + 1) % 10, y, n, n))
links.append(Link(x, y, 1, (x + 1) % 10, (y + 1) % 10, s, s))
links.append(Link(x, y, 2, x, (y + 1) % 10, n, n))
links.append(Link(x, y, 3, (x - 1) % 10, y, s, s))
links.append(Link(x, y, 4, (x - 1) % 10, (y - 1) % 10, n, n))
links.append(Link(x, y, 5, x, (y - 1) % 10, s, s))
r = Router(links, False, 100, 1024)
chips.append(Chip(x, y, processors, r, _sdram, ip))
self.machine = Machine(chips)
#######################################################################
# Setting up graph and graph_mapper #
#######################################################################
self.vertices = list()
self.vertex1 = T_MachineVertex(0, 1,
get_resources_used_by_atoms(0, 1, []),
"First vertex")
self.vertex2 = T_MachineVertex(1, 5,
get_resources_used_by_atoms(1, 5, []),
"Second vertex")
self.vertex3 = T_MachineVertex(5, 10,
get_resources_used_by_atoms(5, 10, []),
"Third vertex")
self.vertex4 = T_MachineVertex(
10, 100, get_resources_used_by_atoms(10, 100, []), "Fourth vertex")
self.vertices.append(self.vertex1)
self.vertices.append(self.vertex2)
self.vertices.append(self.vertex3)
self.vertices.append(self.vertex4)
self.edges = list()
self.graph = MachineGraph(self.vertices, self.edges)
self.graph_mapper = GraphMapper()
self.graph_mapper.add_vertices(self.vertices)
def test_simple_spec(self):
# Create a sdram just to set max chip size
SDRAM(1000)
# Write a data spec to execute
temp_spec = mktemp()
spec_writer = io.FileIO(temp_spec, "w")
spec = DataSpecificationGenerator(spec_writer)
spec.reserve_memory_region(0, 100)
spec.reserve_memory_region(1, 200, empty=True)
spec.reserve_memory_region(2, 4)
spec.reserve_memory_region(3, 12, reference=1)
spec.reference_memory_region(4, 2)
spec.switch_write_focus(0)
spec.write_array([0, 1, 2])
spec.set_write_pointer(20)
spec.write_value(4)
spec.switch_write_focus(2)
spec.write_value(3)
spec.set_write_pointer(0)
spec.write_value(10)
spec.end_specification()
# Execute the spec
spec_reader = io.FileIO(temp_spec, "r")
executor = DataSpecificationExecutor(spec_reader, 400)
executor.execute()
# Test the size
header_and_table_size = (constants.MAX_MEM_REGIONS + 2) * 4
self.assertEqual(executor.get_constructed_data_size(),
header_and_table_size + 100 + 200 + 4 + 12)
# Test the unused regions
for region in range(5, constants.MAX_MEM_REGIONS):
self.assertIsNone(executor.get_region(region))
# Test region 0
region_0 = executor.get_region(0)
self.assertEqual(region_0.allocated_size, 100)
self.assertEqual(region_0.max_write_pointer, 24)
self.assertFalse(region_0.unfilled)
self.assertIsNone(region_0.reference)
self.assertEqual(region_0.region_data[:region_0.max_write_pointer],
struct.pack("<IIIIII", 0, 1, 2, 0, 0, 4))
# Test region 1
region_1 = executor.get_region(1)
self.assertIsInstance(region_1, MemoryRegionReal)
self.assertEqual(region_1.allocated_size, 200)
self.assertTrue(region_1.unfilled)
self.assertIsNone(region_1.reference)
# Test region 2
region_2 = executor.get_region(2)
self.assertIsInstance(region_2, MemoryRegionReal)
self.assertEqual(region_2.allocated_size, 4)
self.assertIsNone(region_2.reference)
self.assertEqual(region_2.region_data, struct.pack("<I", 10))
# Test region 3
region_3 = executor.get_region(3)
self.assertIsInstance(region_3, MemoryRegionReal)
self.assertEqual(region_3.allocated_size, 12)
self.assertEqual(region_3.reference, 1)
self.assertEqual(executor.referenceable_regions, [3])
# Test region 4
region_4 = executor.get_region(4)
self.assertIsInstance(region_4, MemoryRegionReference)
self.assertEqual(region_4.ref, 2)
self.assertEqual(executor.references_to_fill, [4])
# Test the pointer table
table = executor.get_pointer_table(0)
self.assertEqual(len(table), constants.MAX_MEM_REGIONS)
self.assertEqual(table[0], header_and_table_size)
self.assertEqual(table[1], header_and_table_size + 100)
self.assertEqual(table[2], header_and_table_size + 300)
self.assertEqual(table[3], header_and_table_size + 304)
# 4 is also 0 because it is a reference
for region in range(4, constants.MAX_MEM_REGIONS):
self.assertEqual(table[region], 0)
# Test the header
header = executor.get_header()
self.assertEqual(len(header), 2)
self.assertEqual(header[0], constants.APPDATA_MAGIC_NUM)
self.assertEqual(header[1], constants.DSE_VERSION)