def test_read_refs_into_cache_set_associative_lru(self): """read_refs_into_cache should work for set associative LRU cache""" refs = sim.get_addr_refs( word_addrs=TestReadRefs.WORD_ADDRS, num_addr_bits=8, num_tag_bits=5, num_index_bits=2, num_offset_bits=1) cache, ref_statuses = sim.read_refs_into_cache( refs=refs, num_sets=4, num_blocks_per_set=3, num_words_per_block=2, num_index_bits=2, replacement_policy='lru') nose.assert_dict_equal(cache, { '00': [ {'tag': '01011', 'data': [88, 89]} ], '01': [ {'tag': '00000', 'data': [2, 3]}, {'tag': '00101', 'data': [42, 43]}, {'tag': '10111', 'data': [186, 187]} ], '10': [ {'tag': '10110', 'data': [180, 181]}, {'tag': '00101', 'data': [44, 45]}, {'tag': '11111', 'data': [252, 253]} ], '11': [ {'tag': '10111', 'data': [190, 191]}, {'tag': '00001', 'data': [14, 15]}, ] }) nose.assert_set_equal(self.get_hits(ref_statuses), {3, 6, 8})
def test_get_addr_refs(): """get_addr_refs should return correct reference data""" word_addrs = [3, 180, 44, 253] refs = sim.get_addr_refs( word_addrs=word_addrs, num_addr_bits=8, num_tag_bits=4, num_index_bits=3, num_offset_bits=1) ref = refs[1] nose.assert_equal(len(refs), len(word_addrs)) nose.assert_equal(ref.word_addr, 180) nose.assert_equal(ref.bin_addr, '10110100') nose.assert_equal(ref.tag, '1011') nose.assert_equal(ref.index, '010') nose.assert_equal(ref.offset, '0')
def test_display_addr_refs_no_offset(): """should display n/a for offset when there are no offset bits""" refs = sim.get_addr_refs( word_addrs=WORD_ADDRS, num_addr_bits=8, num_tag_bits=4, num_index_bits=4, num_offset_bits=0) ref_statuses = ['miss'] * 12 out = io.StringIO() with contextlib.redirect_stdout(out): sim.display_addr_refs(refs, ref_statuses) table_output = out.getvalue() nose.assert_regexp_matches( table_output, r'\s*{}\s*{}\s*{}'.format( '\d\d', 'n/a', 'miss'))
def test_read_refs_into_cache_fully_associative_mru(self): """read_refs_into_cache should work for fully associative MRU cache""" refs = sim.get_addr_refs( word_addrs=TestReadRefs.WORD_ADDRS, num_addr_bits=8, num_tag_bits=7, num_index_bits=0, num_offset_bits=1) cache, ref_statuses = sim.read_refs_into_cache( refs=refs, num_sets=1, num_blocks_per_set=4, num_words_per_block=2, num_index_bits=0, replacement_policy='mru') nose.assert_dict_equal(cache, { '0': [ {'tag': '0000001', 'data': [2, 3]}, {'tag': '1111110', 'data': [252, 253]}, {'tag': '0010101', 'data': [42, 43]}, {'tag': '0000111', 'data': [14, 15]} ] }) nose.assert_set_equal(self.get_hits(ref_statuses), {3, 8})
def test_read_refs_into_cache_direct_mapped_lru(self): """read_refs_into_cache should work for direct-mapped LRU cache""" word_addrs = [0, 8, 0, 6, 8] refs = sim.get_addr_refs( word_addrs=word_addrs, num_addr_bits=4, num_tag_bits=2, num_index_bits=2, num_offset_bits=0) cache, ref_statuses = sim.read_refs_into_cache( refs=refs, num_sets=4, num_blocks_per_set=1, num_words_per_block=1, num_index_bits=2, replacement_policy='lru') nose.assert_dict_equal(cache, { '00': [ {'tag': '10', 'data': [8]} ], '01': [], '10': [ {'tag': '01', 'data': [6]}, ], '11': [] }) nose.assert_set_equal(self.get_hits(ref_statuses), set())
def test_display_addr_refs(): """should display table of address references""" refs = sim.get_addr_refs( word_addrs=WORD_ADDRS, num_addr_bits=8, num_tag_bits=5, num_index_bits=2, num_offset_bits=1) ref_statuses = ['miss', 'miss', 'HIT', 'miss'] out = io.StringIO() with contextlib.redirect_stdout(out): sim.display_addr_refs(refs, ref_statuses) table_output = out.getvalue() num_cols = 6 col_width = TABLE_WIDTH // num_cols nose.assert_regexp_matches( table_output, r'{}\s*{}\s*{}\s*{}\s*{}\s*{}\n{}'.format( 'WordAddr'.rjust(col_width), 'BinAddr'.rjust(col_width), 'Tag'.rjust(col_width), 'Index'.rjust(col_width), 'Offset'.rjust(col_width), 'Hit/Miss'.rjust(col_width), ('-' * TABLE_WIDTH))) nose.assert_regexp_matches( table_output, r'{}\s*{}\s*{}\s*{}\s*{}\s*{}'.format( '253'.rjust(col_width), '1111 1101'.rjust(col_width), '11111'.rjust(col_width), '10'.rjust(col_width), '1'.rjust(col_width), 'HIT'.rjust(col_width)))