def doPIM(pimNum, prevRtr):
sst.pushNamePrefix("pim%d"%(pimNum))
#make the router
rtr = sst.Component("pimRtr" + str(pimNum), "merlin.hr_router")
rtr.addParams(routerParams)
rtr.addParams({"id" : pimNum+1})
nextPort = 2 #0,1 are reserved for router-to-router
nextAddr = (pimNum+1)*localPorts # Merlin-level network address
#make the quads
for x in range(PIMQuads):
doQuad(x, 4, rtr, nextPort, nextAddr)
nextPort += 1
nextAddr += 1
# real DC
doDC(rtr, nextPort, nextAddr, pimNum)
nextPort += 1
nextAddr += 1
#fake DCs
for x in range(fakePIM_DC):
doFakeDC(rtr, nextPort, nextAddr, pimNum)
nextPort += 1
nextAddr += 1
# connect to chain
wrapLink = sst.Link("p%d"%pimNum)
wrapLink.connect((prevRtr,"port0", netLat),
(rtr, "port1", netLat))
sst.popNamePrefix()
return rtr
def doVS(num, cpu) :
sst.pushNamePrefix("cube%d"%num)
ll = sst.Component("logicLayer", "VaultSimC.logicLayer")
ll.addParams ({
"clock" : """500Mhz""",
"vaults" : str(vaultsPerCube),
"llID" : """0""",
"bwlimit" : """32""",
"LL_MASK" : """0""",
"terminal" : """1"""
})
fromCPU = sst.Link("link_cpu_cube");
fromCPU.connect((cpu, "cube_link", ccLat),
(ll, "toCPU", ccLat))
#make vaults
for x in range(0, vaultsPerCube):
v = sst.Component("ll.Vault"+str(x), "VaultSimC.VaultSimC")
v.addParams({
"clock" : """750Mhz""",
"VaultID" : str(x),
"numVaults2" : math.log(vaultsPerCube,2)
})
ll2V = sst.Link("link_ll_vault" + str(x))
ll2V.connect((ll,"bus_" + str(x), "1ns"),
(v, "bus", "1ns"))
sst.popNamePrefix()
def doVS(num, cpu):
sst.pushNamePrefix("cube%d" % num)
ll = sst.Component("logicLayer", "VaultSimC.logicLayer")
ll.addParams({
"clock": """500Mhz""",
"vaults": str(vaultsPerCube),
"llID": """0""",
"bwlimit": """32""",
"LL_MASK": """0""",
"terminal": """1"""
})
ll.enableStatistics(["BW_recv_from_CPU"], {
"type": "sst.AccumulatorStatistic",
"rate": "0 ns"
})
fromCPU = sst.Link("link_cpu_cube")
fromCPU.connect((cpu, "cube_link", ccLat), (ll, "toCPU", ccLat))
#make vaults
for x in range(0, vaultsPerCube):
v = sst.Component("ll.Vault" + str(x), "VaultSimC.VaultSimC")
v.addParams({
"clock": """750Mhz""",
"VaultID": str(x),
"numVaults2": math.log(vaultsPerCube, 2)
})
v.enableStatistics(["Mem_Outstanding"], {
"type": "sst.AccumulatorStatistic",
"rate": "0 ns"
})
ll2V = sst.Link("link_ll_vault" + str(x))
ll2V.connect((ll, "bus_" + str(x), "1ns"), (v, "bus", "1ns"))
sst.popNamePrefix()
def doPIM(pimNum, prevRtr):
sst.pushNamePrefix("pim%d" % (pimNum))
#make the router
rtr = sst.Component("pimRtr" + str(pimNum), "merlin.hr_router")
rtr.addParams(routerParams)
rtr.addParams({"id": pimNum + 1})
nextPort = 2 #0,1 are reserved for router-to-router
nextAddr = (pimNum + 1) * localPorts # Merlin-level network address
#make the quads
for x in range(PIMQuads):
doQuad(x, 4, rtr, nextPort, nextAddr)
nextPort += 1
nextAddr += 1
# real DC
doDC(rtr, nextPort, nextAddr, pimNum)
nextPort += 1
nextAddr += 1
#fake DCs
for x in range(fakePIM_DC):
doFakeDC(rtr, nextPort, nextAddr, pimNum)
nextPort += 1
nextAddr += 1
# connect to chain
wrapLink = sst.Link("p%d" % pimNum)
wrapLink.connect((prevRtr, "port0", netLat), (rtr, "port1", netLat))
sst.popNamePrefix()
return rtr
def build(self, nID):
sst.pushNamePrefix("group%d" % nID)
bridge = sst.Component("bridge", "merlin.Bridge")
bridge.addParams({
"translator": "memHierarchy.MemNetBridge",
"debug": 0,
"debug_level": 0,
"network_bw": self.netCfg.cfg["bandwidth"],
})
self.buildGroup(nID, bridge)
ret = (bridge, "network1", self.netCfg.cfg["latency"])
sst.popNamePrefix()
return ret
def build(self, nID, extraKeys):
if self.groupInfo.isDone(self.config):
self.next_group_id += 1
self.groupInfo = self.GroupInfo(self.next_group_id)
sst.pushNamePrefix("g%d" % self.groupInfo.groupNum)
nodeType = self.groupInfo.nextItem(self.config)
if nodeType == EndpointCreator._CORE:
ret = self.buildCore(nID)
elif nodeType == EndpointCreator._L3:
ret = self.buildL3(nID)
elif nodeType == EndpointCreator._MEMORY:
ret = self.buildMemory(nID)
else:
print("Unknown Next item type: ", nodeType)
sst.exit(1)
sst.popNamePrefix()
return ret
def doCPU():
sst.pushNamePrefix("cpu")
# make the router
rtr = sst.Component("cpuRtr", "merlin.hr_router")
rtr.addParams(routerParams)
rtr.addParams({"id" : 0})
nextPort = 2 #0,1 are reserved for router-to-router
nextAddr = 0 # Merlin-level network address
#make the quads
for x in range(CPUQuads):
doQuad(x, 4, rtr, nextPort, nextAddr)
nextPort += 1
nextAddr += 1
#fake DCs
for x in range(fakeCPU_DC):
doFakeDC(rtr, nextPort, nextAddr, -1)
nextPort += 1
nextAddr += 1
sst.popNamePrefix()
return rtr
def doCPU():
sst.pushNamePrefix("cpu")
# make the router
rtr = sst.Component("cpuRtr", "merlin.hr_router")
rtr.addParams(routerParams)
rtr.addParams({"id": 0})
nextPort = 2 #0,1 are reserved for router-to-router
nextAddr = 0 # Merlin-level network address
#make the quads
for x in range(CPUQuads):
doQuad(x, 4, rtr, nextPort, nextAddr)
nextPort += 1
nextAddr += 1
#fake DCs
for x in range(fakeCPU_DC):
doFakeDC(rtr, nextPort, nextAddr, -1)
nextPort += 1
nextAddr += 1
sst.popNamePrefix()
return rtr
def doVS(num, cpu):
sst.pushNamePrefix("cube%d" % num)
ll = sst.Component("logicLayer", "VaultSimC.logicLayer")
ll.addParams(
{
"clock": """500Mhz""",
"vaults": str(vaultsPerCube),
"llID": """0""",
"bwlimit": """32""",
"LL_MASK": """0""",
"terminal": """1""",
}
)
ll.enableStatistics(["BW_recv_from_CPU"], {"type": "sst.AccumulatorStatistic", "rate": "0 ns"})
fromCPU = sst.Link("link_cpu_cube")
fromCPU.connect((cpu, "cube_link", ccLat), (ll, "toCPU", ccLat))
# make vaults
for x in range(0, vaultsPerCube):
v = sst.Component("ll.Vault" + str(x), "VaultSimC.VaultSimC")
v.addParams({"clock": """750Mhz""", "VaultID": str(x), "numVaults2": math.log(vaultsPerCube, 2)})
v.enableStatistics(["Mem_Outstanding"], {"type": "sst.AccumulatorStatistic", "rate": "0 ns"})
ll2V = sst.Link("link_ll_vault" + str(x))
ll2V.connect((ll, "bus_" + str(x), "1ns"), (v, "bus", "1ns"))
sst.popNamePrefix()
def doQuad(quad, cores, rtr, rtrPort, netAddr):
sst.pushNamePrefix("q%d"%quad)
bus = sst.Component("membus", "memHierarchy.Bus")
bus.addParams({
"bus_frequency" : clock,
"bus_latency_cycles" : 1,
})
for x in range(cores):
core = 4*quad + x
# make the core
if (useAriel == 0):
coreObj = sst.Component("cpu_%d"%core,"memHierarchy.streamCPU")
coreObj.addParams(cpuParams)
# make l1
l1id = sst.Component("l1cache_%d"%core, "memHierarchy.Cache")
l1id.addParams({
"coherence_protocol": coherence_protocol,
"cache_frequency": clock,
"replacement_policy": "lru",
"cache_size": "8KB",
"associativity": 8,
"cache_line_size": 64,
"low_network_links": 1,
"access_latency_cycles": 2,
"L1": 1,
"statistics": 1,
"debug": memDebug,
"debug_level" : 6,
})
l1id.addParams(l1PrefetchParams)
#connect L1 & Core
if useAriel:
arielL1Link = sst.Link("core_cache_link_%d"%core)
portName = "cache_link_" + str(coreCtr.nextPort())
arielL1Link.connect((ariel, portName,
busLat),
(l1id, "high_network_0", busLat))
else:
coreL1Link = sst.Link("core_cache_link_%d"%core)
coreL1Link.connect((coreObj, "mem_link", busLat),
(l1id, "high_network_0", busLat))
membusLink = sst.Link("cache_bus_link_%d"%core)
membusLink.connect((l1id, "low_network_0", busLat), (bus, "high_network_%d"%x, busLat))
#make the L2 for the quad cluster
l2 = sst.Component("l2cache_nid%d"%netAddr, "memHierarchy.Cache")
l2.addParams({
"coherence_protocol": coherence_protocol,
"cache_frequency": l2clock,
"replacement_policy": "lru",
"cache_size": "128KB",
"associativity": 16,
"cache_line_size": 64,
"access_latency_cycles": 23,
"low_network_links": 1,
"high_network_links": 1,
"mshr_num_entries" : 4096, #64, # TODO: Cesar will update
"L1": 0,
"directory_at_next_level": 1,
"network_address": netAddr,
"network_bw": coreNetBW,
"statistics": 1,
"debug_level" : 6,
"debug": memDebug
})
l2.addParams(l2PrefetchParams)
link = sst.Link("l2cache_%d_link"%quad)
link.connect((l2, "high_network_0", busLat), (bus, "low_network_0", busLat))
link = sst.Link("l2cache_%d_netlink"%quad)
link.connect((l2, "directory", netLat), (rtr, "port%d"%(rtrPort), netLat))
sst.popNamePrefix()
def doQuad(quad, cores, rtr, rtrPort, netAddr):
sst.pushNamePrefix("q%d" % quad)
bus = sst.Component("membus", "memHierarchy.Bus")
bus.addParams({
"bus_frequency": clock,
"bus_latency_cycles": 1,
})
for x in range(cores):
core = 4 * quad + x
# make the core
if (useAriel == 0):
coreObj = sst.Component("cpu_%d" % core, "memHierarchy.streamCPU")
coreObj.addParams(cpuParams)
# make l1
l1id = sst.Component("l1cache_%d" % core, "memHierarchy.Cache")
l1id.addParams({
"coherence_protocol": coherence_protocol,
"cache_frequency": clock,
"replacement_policy": "lru",
"cache_size": "8KB",
"associativity": 8,
"cache_line_size": 64,
"low_network_links": 1,
"access_latency_cycles": 2,
"L1": 1,
"statistics": 1,
"debug": memDebug,
"debug_level": 6,
})
l1id.addParams(l1PrefetchParams)
#connect L1 & Core
if useAriel:
arielL1Link = sst.Link("core_cache_link_%d" % core)
portName = "cache_link_" + str(coreCtr.nextPort())
arielL1Link.connect((ariel, portName, busLat),
(l1id, "high_network_0", busLat))
else:
coreL1Link = sst.Link("core_cache_link_%d" % core)
coreL1Link.connect((coreObj, "mem_link", busLat),
(l1id, "high_network_0", busLat))
membusLink = sst.Link("cache_bus_link_%d" % core)
membusLink.connect((l1id, "low_network_0", busLat),
(bus, "high_network_%d" % x, busLat))
#make the L2 for the quad cluster
l2 = sst.Component("l2cache_nid%d" % netAddr, "memHierarchy.Cache")
l2.addParams({
"coherence_protocol": coherence_protocol,
"cache_frequency": l2clock,
"replacement_policy": "lru",
"cache_size": "128KB",
"associativity": 16,
"cache_line_size": 64,
"access_latency_cycles": 23,
"low_network_links": 1,
"high_network_links": 1,
"mshr_num_entries": 4096, #64, # TODO: Cesar will update
"L1": 0,
"directory_at_next_level": 1,
"network_address": netAddr,
"network_bw": coreNetBW,
"statistics": 1,
"debug_level": 6,
"debug": memDebug
})
l2.addParams(l2PrefetchParams)
link = sst.Link("l2cache_%d_link" % quad)
link.connect((l2, "high_network_0", busLat),
(bus, "low_network_0", busLat))
link = sst.Link("l2cache_%d_netlink" % quad)
link.connect((l2, "directory", netLat),
(rtr, "port%d" % (rtrPort), netLat))
sst.popNamePrefix()
connect("rtr_neg_%d"%next_ring_stop,
router_map["rtr.%d"%next_ring_stop], "port1",
router_map["rtr.%d"%(next_ring_stop-1)], "port0", config.ring_latency)
else:
# Middle stops
connect("rtr_pos_%d"%next_ring_stop,
router_map["rtr.%d"%next_ring_stop], "port0",
router_map["rtr.%d"%(next_ring_stop+1)], "port1", config.ring_latency)
connect("rtr_neg_%d"%next_ring_stop,
router_map["rtr.%d"%next_ring_stop], "port1",
router_map["rtr.%d"%(next_ring_stop-1)], "port0", config.ring_latency)
for next_group in range(config.groups):
print "Configuring core and memory controller group %d..."%next_group
sst.pushNamePrefix("g%d"%next_group)
# Connect Cores & caches
for next_active_core in range(config.cores_per_group):
# Connect L3 cache blocks to ring
for next_l3_cache_block in range(config.l3_cache_per_core):
print "Creating L3 cache block %d..."%(next_l3_cache_id)
l3cache = sst.Component("l3cache_%d"%(next_l3_cache_id), "memHierarchy.Cache")
l3cache.addParams(config.getL3Params())
l3cache.addParams({
"network_address" : next_network_id,
"slice_id" : next_l3_cache_id
})
connect("l3_%d_link"%next_l3_cache_id,
