def __call__(cls, name, parent, *args, **kwargs): # @NoSelf # Derive the hierarhical qualified_name of the component if parent is not None: qualified_name = parent.qualified_name + '/' + name else: qualified_name = '/' + name # Get the initialization arguments p = inspect.getargspec(cls.__init__) initializers = p[0] defaults = p[3] if defaults: # Add all the arguments that have a default value to the kwargs for arg in zip(reversed(initializers), reversed(defaults)): if arg[0] not in kwargs: kwargs[arg[0]] = arg[1] try: configurator = RequiredVariable('Configurator') # Update the dictionary of passed arguments configurator.update_config(qualified_name, kwargs) except KeyError: pass obj = cls.__new__(cls) obj.qualified_name = qualified_name obj.__init__(name, parent, **kwargs) return obj
def __init__(self, name, producer, init=None): self._tracer = RequiredVariable('VCDTracer') self._name = name self._init = init self._code = self._tracer.add_trace(self) self._producer = producer self._val = None
def simarch_inst_start(): """Mark globaly that the simulator is instantiating an architecture at the moment. This flag is removed by calling simarch_inst_stop() function. """ sim = RequiredVariable('Simulator') sim.arch_inst += 1
def __init__(self, sim): self.simulator = sim self.name = 'Scheduler' greenlet.__init__(self) configurator = RequiredVariable('Configurator') if configurator['sys.scheduler', 'log_task_switching', False]: self.settrace(self.callback)
class VCDTrace(): def changed(self): # return self._producer.trace_val_updated val = self._producer.trace_val(self._name) if self._val != val: return True else: return False def print_val(self): self._val = self._producer.trace_val(self._name) self._print_val() def print_init_val(self): self._val = self._init if self._val is not None: self._print_val() def _print_val(self): if isinstance(self._val, bool): self._tracer.vcdfile.write("b{0} {1}\n".format( int(self._val), self._code)) elif hasattr(self._val, 'bitstr'): self._tracer.vcdfile.write("b{0} {1}\n".format( self._val.bitstr(), self._code)) else: # default to 'string' self._tracer.vcdfile.write("s{0} {1}\n".format( str(self._val).replace(' ', '').replace("'", ""), self._code)) def print_var_declaration(self): name = self._name = self._name.replace(':', '_').replace('[', '_').replace( ']', '') if isinstance(self._val, bool): s = "$var wire 1 {0} {1} $end\n".format(self._code, name) elif hasattr(self._val, 'bitstr'): str_val = self._val.bitstr() if len(str_val) == 3: s = "$var wire 1 {0} {1} $end\n".format(self._code, name) else: s = "$var wire {0} {1} {2} $end\n".format( len(str_val) - 2, self._code, name) else: # default to 'string' s = "$var real 1 {0} {1} $end\n".format(self._code, name) self._tracer.vcdfile.write(s) def __init__(self, name, producer, init=None): self._tracer = RequiredVariable('VCDTracer') self._name = name self._init = init self._code = self._tracer.add_trace(self) self._producer = producer self._val = None
class VCDTrace(): def changed(self): # return self._producer.trace_val_updated val = self._producer.trace_val(self._name) if self._val != val: return True else: return False def print_val(self): self._val = self._producer.trace_val(self._name) self._print_val() def print_init_val(self): self._val = self._init if self._val is not None: self._print_val() def _print_val(self): if isinstance(self._val, bool): self._tracer.vcdfile.write("b{0} {1}\n".format(int(self._val), self._code)) elif hasattr(self._val, 'bitstr'): self._tracer.vcdfile.write("b{0} {1}\n".format(self._val.bitstr(), self._code)) else: # default to 'string' self._tracer.vcdfile.write("s{0} {1}\n".format(str(self._val).replace(' ', '').replace("'", ""), self._code)) def print_var_declaration(self): name = self._name = self._name.replace(':','_').replace('[', '_').replace(']', '') if isinstance(self._val, bool): s = "$var wire 1 {0} {1} $end\n".format(self._code, name) elif hasattr(self._val, 'bitstr'): str_val = self._val.bitstr() if len(str_val) == 3: s = "$var wire 1 {0} {1} $end\n".format(self._code, name) else: s = "$var wire {0} {1} {2} $end\n".format(len(str_val) - 2, self._code, name) else: # default to 'string' s ="$var real 1 {0} {1} $end\n".format(self._code, name) self._tracer.vcdfile.write(s) def __init__(self, name, producer, init=None): self._tracer = RequiredVariable('VCDTracer') self._name = name self._init = init self._code = self._tracer.add_trace(self) self._producer = producer self._val = None
def __init__(self, sim_events): self.configurator = RequiredVariable('Configurator') self.include = self.configurator['Coverage', 'include', []] self.branching = self.configurator['Coverage', 'branching', False] self.out_path = self.configurator[ 'Coverage', 'path', self.configurator['sys', 'output_path', self.configurator['sys', 'project_path'] + "/out/coverage"]] self.project_path = self.configurator['sys', 'project_path'] for i in range(len(self.include)): self.include[i] = self.project_path + "/" + self.include[i] sim_events['run_end'].append(self.coverage_done) self.cov = coverage(include=self.include, branch=self.branching, concurrency='greenlet') self.cov.start()
def __init__(self, sim_events): self.configurator = RequiredVariable('Configurator') self.vcd_filename = self.configurator['VCDTracer', 'filename', 'sydpy.vcd'] self.channel_hrchy = self.configurator['VCDTracer', 'channel_hrchy', True] self.vcd_out_path = self.configurator[ 'VCDTracer', 'path', self.configurator['sys', 'output_path', self.configurator['sys', 'project_path'] + "/out"]] self.timescale = self.configurator['sys', 'timescale', '100ps'] self.trace_deltas = self.configurator['VCDTracer', 'trace_deltas', False] self.max_delta_count = self.configurator['sys.sim', 'max_delta_count', 1000] if (not os.path.isdir(self.vcd_out_path)): os.makedirs(self.vcd_out_path, exist_ok=True) self.vcdfile = open( self.vcd_out_path + "/" + self.vcd_filename + ".tmp", 'w') self.trace_list = [] self.last_code = ['a', 'a', 'a'] # sim_events['run_start'].append(self.writeVcdHeader) sim_events['timestep_start'].append(self.write_timestamp) sim_events['timestep_end'].append(self.write_traces) if self.trace_deltas: sim_events['delta_start'].append(self.write_delta_traces) sim_events['run_end'].append(self.writeVcdHeader) # sim_events['run_end'].append(self.flush) features.Provide('VCDTracer', self)
def simtrig(event): """Register event to trigger pool.""" sim = RequiredVariable('Simulator') sim.trig_pool.add(event)
def __init__(self, name, producer): self._name = name self._producer = producer self._tracer = RequiredVariable('VCDTracer')
def simwait(events=None): """Delay process execution by waiting for events.""" sim = RequiredVariable('Simulator') sim.wait(events)
def simarch_inst(): """Return 0 if no architectures are instantiated right now. Return anything else otherwise""" sim = RequiredVariable('Simulator') return (sim.arch_inst > 0)
def simarch_inst_stop(): """Remove the flag set by simarch_inst_start() function.""" sim = RequiredVariable('Simulator') if sim.arch_inst > 0: sim.arch_inst -= 1
def simtime(): """Get the current simulation time.""" sim = RequiredVariable('Simulator') return sim.time
def simproc_reg(proc): """Register a process with the simulator.""" sim = RequiredVariable('Simulator') sim.proc_reg(proc)
def simdelay_pop(proc): """Remove process from the delay schedule.""" sim = RequiredVariable('Simulator') sim.delay_pool.pop(proc, None)
def simdelay_add(proc, time): """Register process to be scheduled for execution after given time.""" sim = RequiredVariable('Simulator') sim.delay_pool[proc] = time + sim.time
def simupdate(sig): """Register signal for update cycle.""" sim = RequiredVariable('Simulator') sim.update_pool.add(sig)