def test51(self):
'''cvel2 51: test fftshift regridding: frequency mode, width positive'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
# get reference values by running cvel2 with linear interpol
cvel2(mode='frequency',
vis='myinput.ms',
outputvis=outfile,
spw='0,1',
nchan=150,
interpolation='linear',
outframe='BARY')
mytb.open(outfile + '/SPECTRAL_WINDOW')
a = mytb.getcell('CHAN_FREQ')
b = numpy.array(a)
mytb.close()
shutil.rmtree(outfile, ignore_errors=True)
rval = cvel2(mode='frequency',
vis='myinput.ms',
outputvis=outfile,
spw='0,1',
nchan=150,
interpolation='fftshift',
outframe='BARY')
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 150, 0, b)
self.assertTrue(ret[0], ret[1])
def test2(self):
'''cvel2 2: Only input vis set - expected error'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
try:
cvel2(vis = 'myinput.ms')
except Exception:
print 'Expected error!'
def test1(self):
'''cvel2 1: Testing default - expected error'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
try:
cvel2()
except Exception:
print 'Expected error!'
def test2(self):
'''cvel2 2: Only input vis set - expected error'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
try:
cvel2(vis='myinput.ms')
except Exception:
print 'Expected error!'
def test1(self):
'''cvel2 1: Testing default - expected error'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
try:
cvel2()
except Exception:
print 'Expected error!'
def test40(self):
'''cvel2 40: test effect of sign of width parameter: radio velocity mode, width negative'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
mytb.open('myinput.ms/SPECTRAL_WINDOW')
a = mytb.getcell('CHAN_FREQ')
c = qa.constants('c')['value']
mytb.close()
restf = a[0]
bv1 = c * (restf-a[3])/restf
bv2 = c * (restf-a[4])/restf
wv = abs(bv2-bv1)
b = numpy.array([a[3], a[4], a[5]])
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode = 'velocity',
veltype = 'radio',
nchan = 3,
start = str(bv1)+'m/s',
width="-"+str(wv)+'m/s',
restfreq=str(restf)+'Hz'
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 3, 0, b)
self.assertTrue(ret[0],ret[1])
def test42(self):
'''cvel2 42: test effect of sign of width parameter: optical velocity mode, width negative'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
mytb.open('myinput.ms/SPECTRAL_WINDOW')
a = mytb.getcell('CHAN_FREQ')
c = qa.constants('c')['value']
mytb.close()
restf = a[0]
bv1 = c * (restf - a[5]) / a[5]
bv2 = c * (restf - a[4]) / a[4]
wv = abs(bv2 - bv1 + 1.)
bv2 = bv1 + wv
bv3 = bv2 + wv
a4 = restf / (bv2 / c + 1.)
a3 = restf / (bv3 / c + 1.)
b = numpy.array([a3, a4, a[5]])
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode='velocity',
veltype='optical',
nchan=3,
start=str(bv3) + 'm/s',
width='-' + str(wv) + 'm/s',
restfreq=str(restf) + 'Hz')
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 3, 0, b)
self.assertTrue(ret[0], ret[1])
def test14(self):
'''cvel2 14: I/O vis set, input vis with one spws, one field selected, one spws selected,
passall = False, non-existing phase center...'''
self.setUp_vis_a()
myvis = vis_a
os.system('ln -sf ' + myvis + ' myinput.ms')
try:
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
field = '1',
spw = '0',
passall = False,
mode='frequency',
nchan = 2,
start = '150GHz',
width = '3MHz',
outframe = 'BARY',
phasecenter = 12
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 2, 0)
self.assertTrue(ret[0],ret[1])
except:
print "*** Expected error ***"
def test6(self):
'''cvel2 6: I/O vis set, more complex input vis, one field selected, one spw selected, passall = True'''
if testmms:
return
self.setUp_vis_a()
myvis = vis_a
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
field='1',
spw='0',
nchan=32,
start=10,
passall=True)
self.assertNotEqual(rval, False)
# Simulate the passall=True. This MS has fields 0~6
desel = outfile + '.deselected'
split(vis='myinput.ms',
outputvis=desel,
field='0,2,3,4,5,6',
spw='0',
datacolumn='all')
mslocal = mstool()
mslocal.open(outfile, nomodify=False)
mslocal.concatenate(msfile=desel)
mslocal.close()
ret = (verify_ms(outfile, 2, 32, 0))
self.assertTrue(ret[0], ret[1])
def test34(self):
'''cvel2 34: EVLA high-res input MS, 2 spws to combine'''
self.setUp_vis_e()
# os.system('ls -l '+vis_e)
# os.path.exists(vis_e+'/SORTED_TABLE')
#
# # myvis = vis_e
# # os.system('ln -sf ' + myvis + ' myinput.ms')
# rval = cvel2(
# vis = vis_e,
# outputvis = outfile,
# mode = 'velocity',
# restfreq = '6035.092MHz'
# )
# self.assertNotEqual(rval,False)
# ret = verify_ms(outfile, 1, 260, 0)
# self.assertTrue(ret[0],ret[1])
myvis = vis_e
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode = 'velocity',
restfreq = '6035.092MHz'
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 260, 0)
self.assertTrue(ret[0],ret[1])
def test34(self):
'''cvel2 34: EVLA high-res input MS, 2 spws to combine'''
self.setUp_vis_e()
# os.system('ls -l '+vis_e)
# os.path.exists(vis_e+'/SORTED_TABLE')
#
# # myvis = vis_e
# # os.system('ln -sf ' + myvis + ' myinput.ms')
# rval = cvel2(
# vis = vis_e,
# outputvis = outfile,
# mode = 'velocity',
# restfreq = '6035.092MHz'
# )
# self.assertNotEqual(rval,False)
# ret = verify_ms(outfile, 1, 260, 0)
# self.assertTrue(ret[0],ret[1])
myvis = vis_e
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode='velocity',
restfreq='6035.092MHz')
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 260, 0)
self.assertTrue(ret[0], ret[1])
def test53(self):
'''cvel2 53: cvel2 of a field with ephemeris attached and outframe SOURCE'''
self.setUp_vis_g()
myvis = vis_g
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms', outputvis=outfile, outframe='SOURCE')
self.assertTrue(rval)
def test40(self):
'''cvel2 40: test effect of sign of width parameter: radio velocity mode, width negative'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
mytb.open('myinput.ms/SPECTRAL_WINDOW')
a = mytb.getcell('CHAN_FREQ')
c = qa.constants('c')['value']
mytb.close()
restf = a[0]
bv1 = c * (restf - a[3]) / restf
bv2 = c * (restf - a[4]) / restf
wv = abs(bv2 - bv1)
b = numpy.array([a[3], a[4], a[5]])
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode='velocity',
veltype='radio',
nchan=3,
start=str(bv1) + 'm/s',
width="-" + str(wv) + 'm/s',
restfreq=str(restf) + 'Hz')
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 3, 0, b)
self.assertTrue(ret[0], ret[1])
def test6(self):
'''cvel2 6: I/O vis set, more complex input vis, one field selected, one spw selected, passall = True'''
if testmms:
return
self.setUp_vis_a()
myvis = vis_a
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
field = '1',
spw = '0',
nchan = 32,
start = 10,
passall = True
)
self.assertNotEqual(rval,False)
# Simulate the passall=True. This MS has fields 0~6
desel = outfile+'.deselected'
split(vis='myinput.ms',outputvis=desel,field='0,2,3,4,5,6',spw='0',datacolumn='all')
mslocal = mstool()
mslocal.open(outfile, nomodify=False)
mslocal.concatenate(msfile=desel)
mslocal.close()
ret = (verify_ms(outfile, 2, 32, 0))
self.assertTrue(ret[0],ret[1])
def test41(self):
'''cvel2 41: test effect of sign of width parameter: optical velocity mode, width positive'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
mytb.open('myinput.ms/SPECTRAL_WINDOW')
a = mytb.getcell('CHAN_FREQ')
c = qa.constants('c')['value']
mytb.close()
restf = a[0]
bv1 = c * (restf-a[5])/a[5]
bv2 = c * (restf-a[4])/a[4]
wv = abs(bv2-bv1+1.)
bv2 = bv1 + wv
bv3 = bv2 + wv
a4 = restf/(bv2/c+1.)
a3 = restf/(bv3/c+1.)
b = numpy.array([a3, a4, a[5]])
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode = 'velocity',
veltype = 'optical',
nchan = 3,
start = str(bv1)+'m/s',
width=str(wv)+'m/s',
restfreq=str(restf)+'Hz'
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 3, 0, b)
self.assertTrue(ret[0],ret[1])
def test26(self):
'''cvel2 26: SMA input MS, 24 spws to combine, optical velocity mode, 40 output channels'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
lambda0 = 2.99792E8/220398.676E6
lambda1 = 2.99792E8/229586E6
vopt = (lambda1-lambda0)/lambda0 * 2.99792E8
lambda2 = 2.99792E8/(229586E6+1200E3)
vwidth = vopt - (lambda2-lambda0)/lambda0 * 2.99792E8
vopt = vopt-vwidth/2.
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode='velocity',
nchan = 41,
restfreq = '220398.676MHz',
start = str(vopt)+'m/s',
width = str(vwidth)+'m/s',
phasecenter = "J2000 18h25m56.09 -12d04m28.20",
veltype = 'optical'
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 41, 0)
self.assertTrue(ret[0],ret[1])
def test4(self):
'''cvel2 4: I/O vis set, more complex input vis, one field selected'''
self.setUp_vis_a()
myvis = vis_a
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms', outputvis=outfile, field='1')
self.assertNotEqual(rval, False)
ret = (verify_ms(outfile, 1, 64, 0))
self.assertTrue(ret[0], ret[1])
def test3(self):
'''cvel2 3: Input and output vis set'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms', outputvis=outfile)
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 64, 0)
self.assertTrue(ret[0], ret[1])
def test4(self):
'''cvel2 4: I/O vis set, more complex input vis, one field selected'''
self.setUp_vis_a()
myvis = vis_a
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis = 'myinput.ms', outputvis = outfile, field = '1')
self.assertNotEqual(rval,False)
ret = (verify_ms(outfile, 1, 64, 0))
self.assertTrue(ret[0],ret[1])
def test3(self):
'''cvel2 3: Input and output vis set'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis = 'myinput.ms', outputvis = outfile)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 64, 0)
self.assertTrue(ret[0],ret[1])
def test30(self):
'''cvel2 30: SMA input MS, 24 spws to combine, scratch columns, mode channel_b, no regridding'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms', outputvis=outfile, mode="channel_b")
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 2425, 0)
self.assertTrue(ret[0], ret[1])
def test27(self):
'''cvel2 27: SMA input MS, 24 spws to combine, scratch columns, no regridding'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
# no regrid
rval = cvel2(vis='myinput.ms', outputvis=outfile)
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 2440, 0)
self.assertTrue(ret[0], ret[1])
def test53(self):
'''cvel2 53: cvel2 of a field with ephemeris attached and outframe SOURCE'''
self.setUp_vis_g()
myvis = vis_g
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
outframe = 'SOURCE'
)
self.assertTrue(rval)
def test52(self):
'''cvel2 52: test fftshift regridding: radio velocity mode, width positive'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
# get reference values by running cvel2 with linear interpol
cvel2(
mode = 'velocity',
veltype = 'radio',
restfreq = '220398.676MHz',
vis = 'myinput.ms',
outputvis = outfile,
spw = '0,1',
nchan = 150,
interpolation = 'linear',
outframe = 'CMB'
)
mytb.open(outfile+'/SPECTRAL_WINDOW')
a = mytb.getcell('CHAN_FREQ')
b = numpy.array(a)
mytb.close()
shutil.rmtree(outfile, ignore_errors=True)
rval = cvel2(
mode = 'velocity',
veltype = 'radio',
restfreq = '220398.676MHz',
vis = 'myinput.ms',
outputvis = outfile,
spw = '0,1',
nchan = 150,
interpolation = 'fftshift',
outframe = 'CMB'
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 150, 0, b)
self.assertTrue(ret[0],ret[1])
def test31(self):
'''cvel2 31: SMA input MS, 24 spws to combine, scratch columns, mode channel, frame trafo'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode="channel",
outframe="BARY",
phasecenter="J2000 18h25m56.09 -12d04m28.20")
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 2440, 0)
self.assertTrue(ret[0], ret[1])
def test27(self):
'''cvel2 27: SMA input MS, 24 spws to combine, scratch columns, no regridding'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
# no regrid
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 2440, 0)
self.assertTrue(ret[0],ret[1])
def test47(self):
'''cvel2 47: SMA input MS with descending freq, 1 spw, nchan not set'''
self.setUp_vis_f()
myvis = vis_f
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode='channel',
spw='10',
start=98,
width=3)
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 10, 0)
self.assertTrue(ret[0], ret[1])
def test33(self):
'''cvel2 33: SMA input MS, 1 spw, scratch columns, mode channel, no trafo, Hanning smoothing'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
spw='1',
outputvis=outfile,
mode="channel",
outframe="",
hanning=True)
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 128, 0)
self.assertTrue(ret[0], ret[1])
def test29(self):
'''cvel2 29: SMA input MS, 24 spws to combine, scratch columns, channel mode, 31 channels'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode="channel",
start=1500,
width=2,
nchan=31)
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 31, 0)
self.assertTrue(ret[0], ret[1])
def test30(self):
'''cvel2 30: SMA input MS, 24 spws to combine, scratch columns, mode channel_b, no regridding'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode="channel_b"
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 2425, 0)
self.assertTrue(ret[0],ret[1])
def test46(self):
'''cvel2 46: SMA input MS with descending freq, 24 spws, nchan=100'''
self.setUp_vis_f()
myvis = vis_f
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode='channel',
spw='',
start=29,
nchan=100)
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 100, 0)
self.assertTrue(ret[0], ret[1])
def test44(self):
'''cvel2 44: SMA input MS, 2 spws to combine, channel mode, nchan not set'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode='channel',
spw='1,15',
start=198,
width=3,
phasecenter="J2000 18h25m56.09 -12d04m28.20")
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 10, 0)
self.assertTrue(ret[0], ret[1])
def test_preaveraging_exception(self):
''' cvel2 pre-averaging exception not there any longer: check the exception
introduced for CAS-9798, but removed after CAS-9853.'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode='channel',
spw='1',
start=98,
width=3,
phasecenter="J2000 18h25m56.09 -12d04m28.20")
self.assertTrue(rval)
ret = verify_ms(outfile, 1, 10, 0)
def test31(self):
'''cvel2 31: SMA input MS, 24 spws to combine, scratch columns, mode channel, frame trafo'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode="channel",
outframe = "BARY",
phasecenter = "J2000 18h25m56.09 -12d04m28.20"
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 2440, 0)
self.assertTrue(ret[0],ret[1])
def test_preaveraging_exception(self):
''' cvel2 pre-averaging exception: check the exception introduced for CAS-9798'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode='channel',
spw='1',
start=98,
width=3,
phasecenter="J2000 18h25m56.09 -12d04m28.20")
self.assertFalse(rval)
with self.assertRaises(RuntimeError):
ret = verify_ms(outfile, 1, 10, 0)
def test21(self):
'''cvel2 21: SMA input MS, 24 spws to combine, frequency mode, 21 output channels'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode='frequency',
nchan=21,
start='229587.0MHz',
width='1600kHz',
phasecenter="J2000 18h25m56.09 -12d04m28.20")
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 21, 0)
self.assertTrue(ret[0], ret[1])
def test7(self):
'''cvel2 7: I/O vis set, input vis with two spws, one field selected, 2 spws selected,
passall = False'''
self.setUp_vis_c()
myvis = vis_c
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis='myinput.ms',
outputvis=outfile,
field='12', # select Jupiter
spw='0,1', # both available SPWs
passall=False)
self.assertNotEqual(rval, False)
ret = (verify_ms(outfile, 1, 2, 0))
self.assertTrue(ret[0], ret[1])
def test20(self):
'''cvel2 20: SMA input MS, 24 spws to combine, channel mode, 111 output channels'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode='channel',
nchan=111,
start=201,
width=3,
phasecenter="J2000 18h25m56.09 -12d04m28.20")
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 111, 0)
self.assertTrue(ret[0], ret[1])
def test45(self):
'''cvel2 45: SMA input MS, 1 spw, channel mode, nchan not set, negative width'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
mode='channel',
spw='1',
start=29,
width=-3,
phasecenter="J2000 18h25m56.09 -12d04m28.20")
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 10, 0)
self.assertTrue(ret[0], ret[1])
def test7(self):
'''cvel2 7: I/O vis set, input vis with two spws, one field selected, 2 spws selected,
passall = False'''
self.setUp_vis_c()
myvis = vis_c
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
field = '12', # select Jupiter
spw = '0,1', # both available SPWs
passall = False
)
self.assertNotEqual(rval,False)
ret = (verify_ms(outfile, 1, 2, 0))
self.assertTrue(ret[0],ret[1])
def test46(self):
'''cvel2 46: SMA input MS with descending freq, 24 spws, nchan=100'''
self.setUp_vis_f()
myvis = vis_f
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode='channel',
spw='',
start = 29,
nchan = 100
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 100, 0)
self.assertTrue(ret[0],ret[1])
def test29(self):
'''cvel2 29: SMA input MS, 24 spws to combine, scratch columns, channel mode, 31 channels'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode="channel",
start=1500,
width=2,
nchan=31
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 31, 0)
self.assertTrue(ret[0],ret[1])
def test33(self):
'''cvel2 33: SMA input MS, 1 spw, scratch columns, mode channel, no trafo, Hanning smoothing'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
spw='1',
outputvis = outfile,
mode="channel",
outframe = "",
hanning = True
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 128, 0)
self.assertTrue(ret[0],ret[1])
def test47(self):
'''cvel2 47: SMA input MS with descending freq, 1 spw, nchan not set'''
self.setUp_vis_f()
myvis = vis_f
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode='channel',
spw='10',
start = 98,
width=3
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 10, 0)
self.assertTrue(ret[0],ret[1])
def test9(self):
'''cvel2 9: I/O vis set, input vis with two spws, one field selected, 2 spws selected,
passall = False, regridding 2'''
self.setUp_vis_c()
myvis = vis_c
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
field='10',
spw='0,1',
passall=False,
mode='channel',
nchan=1,
start=1)
self.assertNotEqual(rval, False)
ret = (verify_ms(outfile, 1, 1, 0))
self.assertTrue(ret[0], ret[1])
def test8(self):
'''cvel2 8: I/O vis set, input vis with two spws, one field selected, 2 spws selected,
passall = False, regridding 1'''
self.setUp_vis_c()
myvis = vis_c
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis='myinput.ms',
outputvis=outfile,
field='11', # select some other field
spw='0,1', # both available SPWs
passall=False, # regrid
nchan=1,
width=2)
self.assertNotEqual(rval, False)
ret = (verify_ms(outfile, 1, 1, 0))
self.assertTrue(ret[0], ret[1])
def test21(self):
'''cvel2 21: SMA input MS, 24 spws to combine, frequency mode, 21 output channels'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode='frequency',
nchan = 21,
start = '229587.0MHz',
width = '1600kHz',
phasecenter = "J2000 18h25m56.09 -12d04m28.20"
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 21, 0)
self.assertTrue(ret[0],ret[1])
def test44(self):
'''cvel2 44: SMA input MS, 2 spws to combine, channel mode, nchan not set'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode='channel',
spw='1,15',
start = 198,
width = 3,
phasecenter = "J2000 18h25m56.09 -12d04m28.20"
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 10, 0)
self.assertTrue(ret[0],ret[1])
def test45(self):
'''cvel2 45: SMA input MS, 1 spw, channel mode, nchan not set, negative width'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode='channel',
spw='1',
start = 29,
width = -3,
phasecenter = "J2000 18h25m56.09 -12d04m28.20"
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 10, 0)
self.assertTrue(ret[0],ret[1])
def test_mms_heuristics2(self):
'''cvel2 : MMS heuristic tests'''
self.setUp_mms_vis_c()
self.createMMS(vis_c, axis='auto', scans='8,11', spws='0,1')
try:
rval = cvel2(vis=self.testmms,
outputvis=outfile,
field='5,6',
spw='0,1',
passall=False,
mode='frequency',
nchan=2,
start='4.8101 GHz',
width='50 MHz',
outframe='')
except Exception:
print 'Expected error!'
def test20(self):
'''cvel2 20: SMA input MS, 24 spws to combine, channel mode, 111 output channels'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode='channel',
nchan = 111,
start = 201,
width = 3,
phasecenter = "J2000 18h25m56.09 -12d04m28.20"
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 111, 0)
self.assertTrue(ret[0],ret[1])
def test10(self):
'''cvel210: I/O vis set, input vis with two spws, one field selected, 2 spws selected, passall = False, regridding 3...'''
self.setUp_vis_c()
myvis = vis_c
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
field='9',
spw='0,1',
passall=False,
mode='frequency',
nchan=1,
start='4.8351GHz',
width='50MHz')
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 1, 0)
self.assertTrue(ret[0], ret[1])
def test36(self):
'''cvel2 36: test effect of sign of width parameter: channel mode, width negative'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
mytb.open('myinput.ms/SPECTRAL_WINDOW')
a = mytb.getcell('CHAN_FREQ')
b = numpy.array([a[1], a[2], a[3]])
mytb.close()
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
nchan=3,
start=3,
width=-1)
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 3, 0, b)
self.assertTrue(ret[0], ret[1])
def test16(self):
'''cvel2 16: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...'''
self.setUp_vis_a()
myvis = vis_a
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis='myinput.ms',
outputvis=outfile,
field='2,3',
spw='0',
passall=False,
mode='channel',
nchan=10,
start=2,
outframe='lsrd',
phasecenter=2)
self.assertNotEqual(rval, False)
ret = verify_ms(outfile, 1, 10, 0)
self.assertTrue(ret[0], ret[1])
def test8(self):
'''cvel2 8: I/O vis set, input vis with two spws, one field selected, 2 spws selected,
passall = False, regridding 1'''
self.setUp_vis_c()
myvis = vis_c
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
field = '11', # select some other field
spw = '0,1', # both available SPWs
passall = False, # regrid
nchan = 1,
width = 2
)
self.assertNotEqual(rval,False)
ret = (verify_ms(outfile, 1, 1, 0))
self.assertTrue(ret[0],ret[1])
def test_mms_heuristics2(self):
'''cvel2 : MMS heuristic tests'''
self.setUp_mms_vis_c()
self.createMMS(vis_c, axis='auto', scans='8,11', spws='0,1')
try:
rval = cvel2(
vis = self.testmms,
outputvis = outfile,
field = '5,6',
spw = '0,1',
passall = False,
mode='frequency',
nchan = 2,
start = '4.8101 GHz',
width = '50 MHz',
outframe = ''
)
except Exception:
print 'Expected error!'
def test9(self):
'''cvel2 9: I/O vis set, input vis with two spws, one field selected, 2 spws selected,
passall = False, regridding 2'''
self.setUp_vis_c()
myvis = vis_c
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
field = '10',
spw = '0,1',
passall = False,
mode='channel',
nchan = 1,
start = 1
)
self.assertNotEqual(rval,False)
ret = (verify_ms(outfile, 1, 1, 0))
self.assertTrue(ret[0],ret[1])
def test10(self):
'''cvel210: I/O vis set, input vis with two spws, one field selected, 2 spws selected, passall = False, regridding 3...'''
self.setUp_vis_c()
myvis = vis_c
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
field = '9',
spw = '0,1',
passall = False,
mode='frequency',
nchan = 1,
start = '4.8351GHz',
width = '50MHz'
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 1, 0)
self.assertTrue(ret[0],ret[1])
def test36(self):
'''cvel2 36: test effect of sign of width parameter: channel mode, width negative'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
mytb.open('myinput.ms/SPECTRAL_WINDOW')
a = mytb.getcell('CHAN_FREQ')
b = numpy.array([a[1], a[2], a[3]])
mytb.close()
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
nchan = 3,
start = 3,
width=-1
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 3, 0, b)
self.assertTrue(ret[0],ret[1])
def test17(self):
'''cvel2 17: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...'''
self.setUp_vis_a()
myvis = vis_a
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = 'cvel-output.ms',
field = '2,3',
spw = '0',
passall = False,
mode='frequency',
nchan = 10,
start = '114.9527GHz',
width = '3.125MHz',
outframe = 'lsrd',
phasecenter = 2)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 10, 0)
self.assertTrue(ret[0],ret[1])