def test_execute_binary(self, spiflash_proc, fpga_uart, uart_timeout,
logfile):
"""
Executes the binary and inspects its UART for "PASS!\r\n" or "FAIL!\r\n".
"""
logger = logging.getLogger(__name__)
test_utils.setup_logfile(logger, logfile)
# Open the UART device and read line by line until we pass or fail.
with fpga_uart.open('rb') as uart_device:
uart_fd = uart_device.fileno()
pattern = re.compile('.*?(PASS!\r\n|FAIL!\r\n)')
match = test_utils.stream_fd_to_log(uart_fd, logger, pattern,
uart_timeout)
if match == None:
pytest.fail(
'Deadline exceeded: did not see PASS! or FAIL! within %ds.',
uart_timeout)
if match.group(1) == 'PASS!\r\n':
logger.debug('Got PASS! from binary.')
else:
pytest.fail('Got FAIL! from binary.')
def test_execute_binary(self, sim_top_earlgrey, uart_timeout, logfile):
"""
Executes the binary and inspects its UART for "PASS!\r\n" or "FAIL!\r\n".
"""
logger = logging.getLogger(__name__)
test_utils.setup_logfile(logger, logfile)
# Verilator will print the string "UART: created /dev/pts/#" to
# indicate which pseudoterminal the UART port is bound to.
uart_match = sim_top_earlgrey.find_in_output(
re.compile('UART: Created (/dev/pts/\\d+)'), 5)
assert uart_match is not None
uart_path = uart_match.group(1)
logger.info("Found UART port at %s." % uart_path)
# Now, open the UART device and read line by line until we pass or
# fail.
with open(uart_path, 'rb') as uart_device:
uart_fd = uart_device.fileno()
pattern = re.compile('.*?(PASS!\r\n|FAIL!\r\n)')
match = test_utils.stream_fd_to_log(uart_fd, logger, pattern,
uart_timeout)
assert match is not None, ('Deadline exceeded: did not see PASS! or FAIL! within %ds.' % uart_timeout)
assert match.group(1).strip() == 'PASS!'