def ROR(): # ROtate Right # Move accumulator val to Reg A RegA.write_register(STA()) # Activate AND output ALU.unset_all() ALU.set_SR(1) # Read result RegADD.clock_data() ROR = RegADD.read_register() # Store result in Accumulator LDA(ROR)
def LSR(): # Logical Shift Right # Move accumulator val to Reg A RegA.write_register(STA()) # Clear the carry, so we shift in zeros CLC() # Activate AND output ALU.unset_all() ALU.set_SR(1) # Read result RegADD.clock_data() SR = RegADD.read_register() # Store result in Accumulator LDA(SR)
