def _sync_db_clock():
" Synchronizes the DB clock to the common reference "
synchronizer = ClockSynchronizer(
self.dboard_clk_control,
self.lmk,
self._spi_ifaces['phase_dac'],
0, # register offset value.
104e6, # TODO don't hardcode
self.ref_clock_freq,
1.9E-12, # fine phase shift. TODO don't hardcode. This should live in the EEPROM
self.INIT_PHASE_DAC_WORD,
0x3,
3, # External PPS pipeline delay from the PPS captured at the FPGA to TDC input
self.slot_idx)
# The radio clock traces on the motherboard are 69 ps longer for Daughterboard B
# than Daughterboard A. We want both of these clocks to align at the converters
# on each board, so adjust the target value for DB B. This is an N3xx series
# peculiarity and will not apply to other motherboards.
trace_delay_offset = {0: 0.0e-0, 1: 69.0e-12}[self.slot_idx]
offset = synchronizer.run(num_meas=[512, 128],
target_offset=trace_delay_offset)
offset_error = abs(offset)
if offset_error > 100e-12:
self.log.error(
"Clock synchronizer measured an offset of {:.1f} ps!".
format(offset_error * 1e12))
raise RuntimeError(
"Clock synchronizer measured an offset of {:.1f} ps!".
format(offset_error * 1e12))
else:
self.log.debug(
"Residual synchronization error: {:.1f} ps.".format(
offset_error * 1e12))
synchronizer = None
self.log.debug("Clock Synchronization Complete!")
def _sync_db_clock(
self,
dboard_ctrl_regs,
master_clock_rate,
ref_clock_freq,
args):
""" Synchronizes the DB clock to the common reference """
reg_offset = 0x200
ext_pps_delay = self.EXT_PPS_DELAY
if args.get('time_source', self.mg_class.default_time_source) == 'sfp0':
reg_offset = 0x400
ref_clock_freq = 62.5e6
ext_pps_delay = 1 # only 1 flop between the WR core output and the TDC input
synchronizer = ClockSynchronizer(
dboard_ctrl_regs,
self.mg_class.lmk,
self._spi_ifaces['phase_dac'],
reg_offset,
master_clock_rate,
ref_clock_freq,
860E-15, # fine phase shift. TODO don't hardcode. This should live in the EEPROM
self.INIT_PHASE_DAC_WORD,
self.PHASE_DAC_SPI_ADDR,
ext_pps_delay,
self.N3XX_INT_PPS_DELAY,
self.slot_idx
)
# The radio clock traces on the motherboard are 69 ps longer for
# Daughterboard B than Daughterboard A. We want both of these clocks to
# align at the converters on each board, so adjust the target value for
# DB B. This is an N3xx series peculiarity and will not apply to other
# motherboards.
trace_delay_offset = {0: 0.0e-0,
1: 69.0e-12}[self.slot_idx]
offset = synchronizer.run(
num_meas=[512, 128],
target_offset=trace_delay_offset)
offset_error = abs(offset)
if offset_error > 100e-12:
self.log.error("Clock synchronizer measured an offset of {:.1f} ps!".format(
offset_error*1e12
))
raise RuntimeError("Clock synchronizer measured an offset of {:.1f} ps!".format(
offset_error*1e12
))
else:
self.log.debug("Residual synchronization error: {:.1f} ps.".format(
offset_error*1e12
))
synchronizer = None # Help garbage collector
self.log.debug("Sample Clock Synchronization Complete!")
def _sync_db_clock(
self,
dboard_ctrl_regs,
master_clock_rate,
ref_clock_freq,
args):
""" Synchronizes the DB clock to the common reference """
reg_offset = 0x200
ext_pps_delay = self.EXT_PPS_DELAY
if args.get('time_source', self.mg_class.default_time_source) == 'sfp0':
reg_offset = 0x400
ref_clock_freq = 62.5e6
ext_pps_delay = 1 # only 1 flop between the WR core output and the TDC input
synchronizer = ClockSynchronizer(
dboard_ctrl_regs,
self.mg_class.lmk,
self._spi_ifaces['phase_dac'],
reg_offset,
master_clock_rate,
ref_clock_freq,
860E-15, # fine phase shift. TODO don't hardcode. This should live in the EEPROM
self.INIT_PHASE_DAC_WORD,
self.PHASE_DAC_SPI_ADDR,
ext_pps_delay,
self.N3XX_INT_PPS_DELAY,
self.slot_idx
)
# The radio clock traces on the motherboard are 69 ps longer for
# Daughterboard B than Daughterboard A. We want both of these clocks to
# align at the converters on each board, so adjust the target value for
# DB B. This is an N3xx series peculiarity and will not apply to other
# motherboards.
trace_delay_offset = {0: 0.0e-0,
1: 69.0e-12}[self.slot_idx]
offset = synchronizer.run(
num_meas=[512, 128],
target_offset=trace_delay_offset)
offset_error = abs(offset)
if offset_error > 100e-12:
self.log.error("Clock synchronizer measured an offset of {:.1f} ps!".format(
offset_error*1e12
))
raise RuntimeError("Clock synchronizer measured an offset of {:.1f} ps!".format(
offset_error*1e12
))
else:
self.log.debug("Residual synchronization error: {:.1f} ps.".format(
offset_error*1e12
))
synchronizer = None # Help garbage collector
self.log.debug("Sample Clock Synchronization Complete!")
def _sync_db_clock():
" Synchronizes the DB clock to the common reference "
reg_offset = 0x200
ext_pps_delay = self.EXT_PPS_DELAY
#from outdated inst of ClockSync
#2.496e9, # lmk_vco_freq
synchronizer = ClockSynchronizer(
self.radio_regs,
self.lmk,
self._spi_ifaces['phase_dac'],
reg_offset,
self.master_clock_rate,
self.ref_clock_freq,
1.9E-12, # fine phase shift. TODO don't hardcode. This should live in the EEPROM
self.INIT_PHASE_DAC_WORD,
self.PHASE_DAC_SPI_ADDR,
ext_pps_delay,
self.N3XX_INT_PPS_DELAY,
self.slot_idx)
# The radio clock traces on the motherboard are 69 ps longer for Daughterboard B
# than Daughterboard A. We want both of these clocks to align at the converters
# on each board, so adjust the target value for DB B. This is an N3xx series
# peculiarity and will not apply to other motherboards.
trace_delay_offset = {0: 0.0e-0,
1: 69.0e-12}[self.slot_idx]
offset = synchronizer.run(
num_meas=[512, 128],
target_offset = trace_delay_offset)
offset_error = abs(offset)
if offset_error > 100e-12:
self.log.error("Clock synchronizer measured an offset of {:.1f} ps!".format(
offset_error*1e12
))
raise RuntimeError("Clock synchronizer measured an offset of {:.1f} ps!".format(
offset_error*1e12
))
else:
self.log.debug("Residual synchronization error: {:.1f} ps.".format(
offset_error*1e12
))
synchronizer = None
self.log.debug("Clock Synchronization Complete!")
def _sync_db_clock():
" Synchronizes the DB clock to the common reference "
reg_offset = 0x200
ext_pps_delay = self.EXT_PPS_DELAY
#from outdated inst of ClockSync
#2.496e9, # lmk_vco_freq
synchronizer = ClockSynchronizer(
self.radio_regs,
self.lmk,
self._spi_ifaces['phase_dac'],
reg_offset,
self.master_clock_rate,
self.ref_clock_freq,
1.9E-12, # fine phase shift. TODO don't hardcode. This should live in the EEPROM
self.INIT_PHASE_DAC_WORD,
self.PHASE_DAC_SPI_ADDR,
ext_pps_delay,
self.N3XX_INT_PPS_DELAY,
self.slot_idx)
# The radio clock traces on the motherboard are 69 ps longer for Daughterboard B
# than Daughterboard A. We want both of these clocks to align at the converters
# on each board, so adjust the target value for DB B. This is an N3xx series
# peculiarity and will not apply to other motherboards.
trace_delay_offset = {0: 0.0e-0, 1: 69.0e-12}[self.slot_idx]
offset = synchronizer.run(num_meas=[512, 128],
target_offset=trace_delay_offset)
offset_error = abs(offset)
if offset_error > 100e-12:
self.log.error(
"Clock synchronizer measured an offset of {:.1f} ps!".
format(offset_error * 1e12))
raise RuntimeError(
"Clock synchronizer measured an offset of {:.1f} ps!".
format(offset_error * 1e12))
else:
self.log.debug(
"Residual synchronization error: {:.1f} ps.".format(
offset_error * 1e12))
synchronizer = None
self.log.debug("Clock Synchronization Complete!")
def _sync_db_clock():
" Synchronizes the DB clock to the common reference "
synchronizer = ClockSynchronizer(
self.dboard_clk_control,
self.lmk,
self._spi_ifaces['phase_dac'],
0, # register offset value.
104e6, # TODO don't hardcode
self.ref_clock_freq,
1.9E-12, # fine phase shift. TODO don't hardcode. This should live in the EEPROM
self.INIT_PHASE_DAC_WORD,
0x3,
3, # External PPS pipeline delay from the PPS captured at the FPGA to TDC input
self.slot_idx)
# The radio clock traces on the motherboard are 69 ps longer for Daughterboard B
# than Daughterboard A. We want both of these clocks to align at the converters
# on each board, so adjust the target value for DB B. This is an N3xx series
# peculiarity and will not apply to other motherboards.
trace_delay_offset = {0: 0.0e-0,
1: 69.0e-12}[self.slot_idx]
offset = synchronizer.run(
num_meas=[512, 128],
target_offset = trace_delay_offset)
offset_error = abs(offset)
if offset_error > 100e-12:
self.log.error("Clock synchronizer measured an offset of {:.1f} ps!".format(
offset_error*1e12
))
raise RuntimeError("Clock synchronizer measured an offset of {:.1f} ps!".format(
offset_error*1e12
))
else:
self.log.debug("Residual synchronization error: {:.1f} ps.".format(
offset_error*1e12
))
synchronizer = None
self.log.debug("Clock Synchronization Complete!")