bitsmake=fpgamakeRuleTemplate % {'partitions': ' '.join(['-s %s' % p for p in options.partition_module]),
'floorplan': os.path.abspath(options.floorplan) if options.floorplan else '',
'xdc': ' '.join(['--xdc=%s' % os.path.abspath(xdc) for xdc in options.constraint]),
'xci': ' '.join(['--xci=%s' % os.path.abspath(xci) for xci in options.xci]),
'sourceTcl': ' '.join(['--tcl=%s' % os.path.abspath(tcl) for tcl in options.tcl]),
'verilog': ' '.join([os.path.abspath(f) for f in options.verilog]),
'cachedir': '--cachedir=%s' % os.path.abspath(options.cachedir) if options.cachedir else ''
}
make.write(makefileTemplate % {'connectaldir': connectaldir,
'bsvpath': ':'.join(list(set([os.path.dirname(os.path.abspath(bsvfile)) for bsvfile in options.bsvfile]
+ [os.path.join(connectaldir, 'bsv')]
+ [os.path.join(connectaldir, 'lib/bsv')]
+ [os.path.join(connectaldir, 'generated/xilinx')]))),
'bsvdefines': util.foldl((lambda e,a: e+' -D '+a), '', bsvdefines),
'boardname': boardname,
'OS': options.os,
'qtused': 'cd jni; qmake ../..; make' if options.qtused else '',
's2hinterface': ' '.join(options.s2hinterface),
'h2sinterface': ' '.join(options.h2sinterface),
'bsvfiles': ' '.join([ os.path.abspath(bsvfile) for bsvfile in options.bsvfile]),
'bsimsource': ' '.join([os.path.abspath(bsimsource) for bsimsource in options.bsimsource]) if options.bsimsource else '',
'includepath': ' '.join(['-I%s' % os.path.dirname(os.path.abspath(source)) for source in options.source]) if options.source else '',
'runsource2': 'RUNSOURCE2=1' if options.source2 else '',
'project_dir': project_dir,
'topbsvfile' : os.path.abspath(topbsv),
'topbsvmod' : dutname,
'dut' : dutname.lower(),
'Dut': dutname,
'clibs': ' '.join(['-l%s' % l for l in options.clib]),
[os.path.join(connectaldir, 'generated/xilinx')],
[os.path.join(connectaldir, 'generated/altera')]]:
for p in l:
if p not in unique_bsvpaths:
unique_bsvpaths.append(p)
if options.protobuf:
protolist = [os.path.abspath(fn) for fn in options.protobuf]
make.write(
makefileTemplate % {
'connectaldir':
connectaldir,
'bsvpath':
':'.join(unique_bsvpaths),
'bsvdefines':
util.foldl((lambda e, a: e + ' -D ' + a), '', bsvdefines),
'boardname':
boardname,
'OS':
options.os,
'qtused':
'cd jni; qmake ../..; make' if options.qtused else '',
'interfaces':
' '.join(options.interfaces),
'bsvfiles':
' '.join([os.path.abspath(bsvfile)
for bsvfile in options.bsvfile]),
'xcifiles':
' '.join([os.path.abspath(xci) for xci in options.xci]),
'bsimsource':
' '.join([
