def test_object_registry(self):
class ABC:
def __init__(self, name):
self.name = name
self.value = 5
uvm_object_utils(ABC)
reg = UVMObjectRegistry(ABC, 'ABC')
abc_obj = reg.create('obj_name')
self.assertEqual(abc_obj.name, 'obj_name')
self.assertEqual(isinstance(abc_obj, ABC), True)
from uvm.reg.uvm_reg_block import UVMRegBlock
from cocotbext.ral.dv_reg_map import DVRegMap
class DVRegBlock(UVMRegBlock):
"""
Overrides the UVMRegBlock::create_map() method to use DVRegMap.
"""
def create_map(self,
name: str,
base_addr: int,
n_bytes: int,
endian: int,
byte_addressing=True) -> Optional[DVRegMap]:
"""
"""
if self.locked is True:
uvm_error("RegModel", "Cannot add map to locked model")
return None
_map = DVRegMap.type_id.create(name, None, self.get_full_name())
_map.configure(self, base_addr, n_bytes, endian, byte_addressing)
self.maps[_map] = True
if self.maps.num() == 1:
self.default_map = _map
return _map
uvm_object_utils(DVRegBlock)
# { req.addr == start_addr
# req.read_write == READ
# req.size == 1
# req.error_pos == 1000
# req.transmit_delay == transmit_del; } )
rsp = []
await self.get_response(rsp)
self.rsp = rsp[0]
uvm_info(self.get_type_name(),
sv.sformatf("%s read : addr = `x{}, data[0] = `x{}",
self.get_sequence_path(), self.rsp.addr, self.rsp.data[0]),
UVM_HIGH)
# endtask
uvm_object_utils(read_byte_seq)
#//------------------------------------------------------------------------------
#//
#// SEQUENCE: read_half_word_seq
#//
#//------------------------------------------------------------------------------
#
#class read_half_word_seq extends ubus_base_sequence
#
# function new(string name="read_half_word_seq")
# super.new(name)
# endfunction
#
# `uvm_object_utils(read_half_word_seq)
else:
adapter.bus2reg(bus_req, rw_access)
data = rw_access.data & (
(1 << bus_width * 8) - 1) # mask the upper bits
rw.status = rw_access.status
# TODO
#if (rw.status == UVM_IS_OK && (^data) === 1'bx):
uvm_debug(
self.get_type_name(),
sv.sformatf("Read 0x%h at 0x%h via map %s: %s...",
data, addrs[i], self.get_full_name(),
str(rw.status)), UVM_VERB_MEM_MAP)
if (rw.status == UVM_NOT_OK):
break
rw.value[val_idx] |= data << curr_byte_ * 8
for i in range(len(addrs)):
addrs[i] = addrs[i] + map_info.mem_range.stride
if (rw.element_kind == UVM_FIELD):
rw.value[val_idx] = (rw.value[val_idx] >>
(n_access_extra)) & ((1 << size) - 1)
uvm_object_utils(DVRegMap)
# MIT License
# Copyright (c) 2021 SystematIC Design BV
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in all
# copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
from uvm.reg.uvm_reg_field import UVMRegField
from uvm.macros.uvm_object_defines import uvm_object_utils
class DVRegField(UVMRegField):
pass
uvm_object_utils(DVRegField)
# MIT License
# Copyright (c) 2021 SystematIC Design BV
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in all
# copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
from uvm.reg.uvm_reg import UVMReg
from uvm.macros.uvm_object_defines import uvm_object_utils
class DVReg(UVMReg):
pass
uvm_object_utils(DVReg)