def test_comp_utils(self): # Class for testing class Dummy: def __init__(self, name, parent): self.name = name self.parent = parent uvm_component_utils(Dummy) self.assertEqual(Dummy.type_name, 'Dummy') print('Dummy.type_name: ' + Dummy.type_name) obj = Dummy.type_id.create('comp', None) self.assertEqual(obj.get_type_name(), 'Dummy')
def test_create_component_by_name(self): cs = UVMCoreService.get() factory = UVMFactory.get() cs.set_factory(factory) class MyTest123(UVMTest): def __init__(self, name, parent): UVMTest.__init__(self, name, parent) uvm_component_utils(MyTest123) test_name = 'MyTest123' uvm_test_top = factory.create_component_by_name( test_name, "", "uvm_test_top", None) self.assertEqual(uvm_test_top.get_full_name(), "uvm_test_top")
#// Unless required by applicable law or agreed to in #// writing, software distributed under the License is #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR #// CONDITIONS OF ANY KIND, either express or implied. See #// the License for the specific language governing #// permissions and limitations under the License. #//---------------------------------------------------------------------- from uvm.seq import UVMSequencer from uvm.tlm1 import UVMBlockingPeekPort from uvm.macros import uvm_component_utils #//------------------------------------------------------------------------------ #// #// CLASS: ubus_slave_sequencer #// #//------------------------------------------------------------------------------ #class ubus_slave_sequencer extends uvm_sequencer #(ubus_transfer); class ubus_slave_sequencer(UVMSequencer): def __init__(self, name, parent): UVMSequencer.__init__(self, name, parent) self.addr_ph_port = UVMBlockingPeekPort("addr_ph_port", self) # endfunction : new #endclass : ubus_slave_sequencer uvm_component_utils(ubus_slave_sequencer)
async def main_phase(self, phase): uvm_info(self.tag, 'main_phase started in child', UVM_MEDIUM) def get_packet(self): uvm_info( "PKTGEN", sv.sformatf("Getting a packet from %s (%s)", self.get_full_name(), self.get_type_name()), UVM_MEDIUM) return super().get_packet() # Use the macro in a class to implement factory registration along with other # utilities (create, get_type_name). To just do factory registration, use the # macro `uvm_object_registry(mygen,"mygen") uvm_component_utils(my_child) class my_top_test(UVMTest): def __init__(self, name="my_top_test", parent=None): super().__init__(name, parent) self.tag = 'MY_TOP_TEST' def build_phase(self, phase): super().build_phase(phase) self.child = my_child.type_id.create('my_child', self) def connect_phase(self, phase): self.def_file = open('uvm_master_log.log', 'w') self.set_report_default_file_hier(self.def_file) self.set_report_severity_action_hier(UVM_INFO, UVM_LOG | UVM_DISPLAY)
#// CONDITIONS OF ANY KIND, either express or implied. See #// the License for the specific language governing #// permissions and limitations under the License. #//---------------------------------------------------------------------- from uvm.base.uvm_component import UVMComponent from uvm.macros import uvm_component_utils #from uvm import * from packet_pkg import packet class gen(UVMComponent): def __init__(self, name, parent): super().__init__(name, parent) def get_packet(self): # use the factory to generate a packet pkt = packet.type_id.create("p", self) # randomize it pkt.randomize() # cast to 'void' removed return pkt # //Use the macro in a class to implement factory registration along with other # //utilities (create, get_type_name). To do only factory registration, use # //the macro `uvm_component_utils(gen,"gen"). uvm_component_utils(gen)
self.test_pass = False self.err_msg += '\nnum_init_reads == 0 in scb' def report_phase(self, phase): if self.test_pass: uvm_info(self.get_type_name(), "** UVM TEST PASSED **", UVM_NONE) else: uvm_fatal(self.get_type_name(), "** UVM TEST FAIL **\n" + self.err_msg) # endfunction #endclass : ubus_example_base_test uvm_component_utils(ubus_example_base_test) #// Read Modify Write Read Test #class test_read_modify_write extends ubus_example_base_test class test_read_modify_write(ubus_example_base_test): def __init__(self, name="test_read_modify_write", parent=None): ubus_example_base_test.__init__(self, name, parent) def build_phase(self, phase): UVMConfigDb.set( self, "ubus_example_tb0.ubus0.masters[0].sequencer.run_phase", "default_sequence", read_modify_write_seq.type_id.get()) UVMConfigDb.set( self, "ubus_example_tb0.ubus0.slaves[0].sequencer.run_phase", "default_sequence", slave_memory_seq.type_id.get())
def __init__(self, name="tb_env", parent=None): super().__init__(name, parent) self.regmodel = None self.apb = None self.predict = None def build_phase(self, phase): if self.regmodel is None: self.regmodel = reg_block_B.type_id.create("regmodel") self.regmodel.build() self.regmodel.lock_model() self.apb = apb_agent.type_id.create("apb", self) self.predict = UVMRegPredictor.type_id.create("predict", self) def connect_phase(self, phase): if self.regmodel.get_parent() is None: self.apb_adapter = reg2apb_adapter("apb_adapter") self.regmodel.default_map.set_sequencer(self.apb.sqr, self.apb_adapter) self.regmodel.default_map.set_auto_predict(0) self.apb.mon.ap.connect(self.predict.bus_in) self.predict.map = self.regmodel.default_map self.predict.adapter = self.apb_adapter uvm_component_utils(tb_env)
from uvm.seq.uvm_sequencer import UVMSequencer from uvm.macros import uvm_component_utils class ram_sequencer(UVMSequencer): # ram_sequence def __init__(self, name, parent=None): UVMSequencer.__init__(self, name, parent) uvm_component_utils(ram_sequencer)
# // respond_to_transfer @cocotb.coroutine def respond_to_transfer(self, resp): if resp.read_write != NOP: print("QQQ slave driver responding to " + resp.convert2string()) self.vif.sig_error <= 0 for i in range(resp.size): if resp.read_write == READ: self.vif.slave_en <= 1 self.vif.sig_data_out <= resp.data[i] if resp.wait_state[i] > 0: self.vif.sig_wait <= 1 for j in range(resp.wait_state[i]): yield RisingEdge(self.vif.sig_clock) self.vif.sig_wait <= 0 yield RisingEdge(self.vif.sig_clock) resp.data[i] = int(self.vif.sig_data) self.vif.slave_en <= 0 self.vif.sig_wait <= 0 # 1'bz self.vif.sig_error <= 0 # 1'bz else: yield Timer(0) # endtask : respond_to_transfer # #endclass : ubus_slave_driver # Provide implementations of virtual methods such as get_type_name and create uvm_component_utils(ubus_slave_driver)
type_name = "UVMAlgorithmicComparator" # // Function: new # // # // Creates an instance of a specialization of this class. # // In addition to the standard uvm_component constructor arguments, ~name~ # // and ~parent~, the constructor takes a handle to a ~transformer~ object, # // which must already be allocated (handles can't be ~null~) and must implement # // the transform() method. # def __init__(self, name, parent=None, transformer=None): super().__init__(name, parent) self.m_transformer = transformer self.comp = UVMInOrderClassComparator("comp", self) self.before_export = UVMAnalysisImp("before_analysis_export", self) self.after_export = UVMAnalysisExport("after_analysis_export", self) def get_type_name(self): return UVMAlgorithmicComparator.type_name def connect_phase(self, phase): self.after_export.connect(self.comp.after_export) def write(self, b): self.comp.before_export.write(self.m_transformer.transform(b)) uvm_component_utils(UVMAlgorithmicComparator)
self.vif.tgd_i <= tr.response_data_tag await RisingEdge(self.vif.clk_i) async def get_and_drive(self, phase): tr = [] # Drives signals with sequences await self.seq_item_port.get_next_item(tr) phase.raise_objection(self, self.tag + "objection") tr = tr[0] await self.feed_data(tr) self.seq_item_port.item_done() phase.drop_objection(self, "wb_pipeline_slave_driver drop objection") self.vif.stb_o <= 0 self.trig.set() async def reset_signals(self): # Hold signals low while reset self.vif.stb_o <= 0 await RisingEdge(self.vif.clk_i) async def trans_executed(self, tr): # uvm_info(self.tag, "Finished Memory Interface read to address : " + str(tr.addr.value), UVM_MEDIUM) tr.convert2string await Timer(0, "NS") uvm_component_utils(wb_pipeline_slave_driver)
# // new - constructor def __init__(self, name, parent): super().__init__(name, parent) self.master_id = 0 self.driver = None self.sequencer = None self.monitor = None def build_phase(self, phase): super().build_phase(phase) self.monitor = ubus_master_monitor.type_id.create("monitor", self) if self.get_is_active() == UVM_ACTIVE: self.driver = ubus_master_driver.type_id.create("driver", self) self.sequencer = ubus_master_sequencer.type_id.create( "sequencer", self) arr = [] if UVMConfigDb.get(self, "*", "master_id", arr) is True: self.master_id = arr[0] UVMConfigDb.set(self, "", "master_id", self.master_id) # connect_phase def connect_phase(self, phase): if self.get_is_active() == UVM_ACTIVE: self.driver.seq_item_port.connect(self.sequencer.seq_item_export) self.sequencer.addr_ph_port.connect(self.monitor.addr_ph_imp) # endfunction : connect_phase uvm_component_utils(ubus_master_agent)
#// http://www.apache.org/licenses/LICENSE-2.0 #// #// Unless required by applicable law or agreed to in #// writing, software distributed under the License is #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR #// CONDITIONS OF ANY KIND, either express or implied. See #// the License for the specific language governing #// permissions and limitations under the License. #//---------------------------------------------------------------------- from uvm.seq import UVMSequencer from uvm.tlm1 import UVMBlockingPeekPort from uvm.macros import uvm_component_utils #//------------------------------------------------------------------------------ #// #// CLASS: ubus_master_sequencer #// #//------------------------------------------------------------------------------ class ubus_master_sequencer(UVMSequencer): def __init__(self, name, parent): UVMSequencer.__init__(self, name, parent) self.addr_ph_port = UVMBlockingPeekPort("addr_ph_port", self) #endclass : ubus_master_sequencer uvm_component_utils(ubus_master_sequencer)
# Check to see if entry in associative array for this address # If not, update the location regardless if read or write. else: data = trans.data[i] uvm_info( self.get_type_name(), sv.sformatf( "%s to empty address...Updating address : %0h with data : %0h", str(trans.read_write), int(trans.addr + i), int(data)), UVM_LOW) self.m_mem_expected[trans.addr + i] = trans.data[i] if trans.read_write == READ: self.num_uninit_reads += 1 elif (trans.read_write == WRITE): self.num_writes += 1 # endfunction : memory_verify # // report_phase # virtual function void report_phase(uvm_phase phase) # if(!disable_scoreboard): # `uvm_info(get_type_name(), # $sformatf("Reporting scoreboard information...\n%s", this.sprint()), UVM_LOW) # end # endfunction : report_phase #endclass : ubus_example_scoreboard uvm_component_utils(ubus_example_scoreboard)
self.ap_before.connect(self.compar.before_export) self.ap_after.connect(self.compar.after_export) async def run_phase(self, phase): phase.raise_objection(self) await Timer(10, "NS") self.ap_before.write(Packet('p_in')) self.ap_after.write(Packet('p_out')) await Timer(10, "NS") pkt_err = Packet('p_err') pkt_err.data = 0x1234 self.ap_before.write(Packet('p_in2')) self.ap_after.write(pkt_err) await Timer(100, "NS") phase.drop_objection(self) uvm_component_utils(ComparatorTest) @cocotb.test() async def test_comparators(dut): cs = UVMCoreService.get() svr = cs.get_report_server() await run_test() num_errors = svr.get_severity_count(UVM_ERROR) if num_errors != 1: raise Exception("There were {} uvm_errors, exp 1".format(num_errors))
class ubus_slave_agent(UVMAgent): # // constructor def __init__(self, name, parent): UVMAgent.__init__(self, name, parent) self.driver = None self.sequencer = None self.monitor = None self.tag = "UBUS_SLAVE_AGENT_" + name # // build_phase def build_phase(self, phase): UVMAgent.build_phase(self, phase) self.monitor = ubus_slave_monitor.type_id.create("u_slv_monitor", self) if self.get_is_active() == UVM_ACTIVE: self.driver = ubus_slave_driver.type_id.create("u_slv_driver", self) self.sequencer = ubus_slave_sequencer.type_id.create("u_slv_sequencer", self) # connect_phase def connect_phase(self, phase): if self.get_is_active() == UVM_ACTIVE: uvm_info(self.tag, "Connecting comps in active mode now", UVM_MEDIUM) self.driver.seq_item_port.connect(self.sequencer.seq_item_export) self.sequencer.addr_ph_port.connect(self.monitor.addr_ph_imp) uvm_component_utils(ubus_slave_agent)
#// All Rights Reserved Worldwide #// #// Licensed under the Apache License, Version 2.0 (the #// "License"); you may not use this file except in #// compliance with the License. You may obtain a copy of #// the License at #// #// http://www.apache.org/licenses/LICENSE-2.0 #// #// Unless required by applicable law or agreed to in #// writing, software distributed under the License is #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR #// CONDITIONS OF ANY KIND, either express or implied. See #// the License for the specific language governing #// permissions and limitations under the License. #// ------------------------------------------------------------- #// from uvm.seq.uvm_sequencer import UVMSequencer from uvm.macros import uvm_component_utils class apb_sequencer(UVMSequencer): # (apb_rw) def __init__(self, name, parent=None): super().__init__(name, parent) uvm_component_utils(apb_sequencer)
self.xfer.data = [] self.ph = USB_TLM_TOKEN self.sync = await self.sock.nb_transport_fw( self.xfer, self.ph, self.delay) if self.sync == uvm_tlm_sync_e.UVM_TLM_COMPLETED: uvm_info("USB/HST/IN/REFUSED", "Device refused the transfer", UVM_LOW) break if self.sync == uvm_tlm_sync_e.UVM_TLM_UPDATED: uvm_info("USB/HST/IN/EARLY", "Device returned bulk data early", UVM_LOW) else: # Wait for the device to reply # TODO wait(ph == USB_TLM_DATA) uvm_info("USB/HST/IN/NORMAL", "IN data returned normally", UVM_LOW) self.ph = USB_TLM_HANDSHAKE self.xfer.status = usb_xfer.ACK self.sync = await self.sock.nb_transport_fw( self.xfer, self.ph, self.delay) assert (self.sync == uvm_tlm_sync_e.UVM_TLM_COMPLETED) done = True uvm_info("USB/HST/IN/DONE", self.xfer.convert2string(), UVM_NONE) phase.drop_objection(self) uvm_component_utils(host)
break self.vif.rw <= 0 # // drive_size def drive_size(self, size): if size == 1: self.vif.sig_size <= 0 elif size == 2: self.vif.sig_size <= 1 elif size == 4: self.vif.sig_size <= 2 elif size == 8: self.vif.sig_size <= 3 # // drive_read_write def drive_read_write(self, rw): uvm_info("MASTER_DRV", "Driving rw-value: " + str(rw), UVM_LOW) if rw == NOP: self.vif.sig_read <= 0 self.vif.sig_write <= 0 elif rw == READ: self.vif.sig_read <= 1 self.vif.sig_write <= 0 elif rw == WRITE: self.vif.sig_read <= 0 self.vif.sig_write <= 1 uvm_component_utils(ubus_master_driver)
UVM_MEDIUM) phase.raise_objection(self) UVMDebug.DEBUG = False self.uvm_report_info("component", "after raising objection", UVM_MEDIUM) await Timer(1, 'ns') uvm_debug(self, 'run_phase', "Objection raised run_phase " + self.get_name()) await Timer(2, 'ns') self.uvm_report_info("component", "hello out there!", UVM_MEDIUM) await Timer(1000, 'ns') self.uvm_report_info("component", "finishing up!", UVM_MEDIUM) phase.drop_objection(self) uvm_component_utils(MyComponent) @cocotb.test() async def simple_trivial_component_test(dut): cc = MyComponent("Top", None) print(cc.get_full_name()) # tpoikela: Required by ghdl cocotb.fork(Clock(dut.clk, 1, "NS").start()) await run_test() sim_time = get_sim_time() await Timer(501, 'ns') if sim_time == 0: raise Exception('Sim time has not progressed')
await RisingEdge(self.vif.i_reset) self.vif.o_so_en <= 0 self.vif.o_so <= 0 self.vif.o_ss_en <= 0 self.vif.o_ss_out <= 0 self.vif.o_sclk_en <= 0 self.vif.o_mo_en <= 0 self.vif.o_mo <= 0 await FallingEdge(self.vif.i_reset) async def drive_transfer(self, tr): #if (self.csr_s.mode_select == 1): # DUT MASTER mode, OVC SLAVE mode #@monitor.new_transfer_started; #for (int i = 0; i < self.csr_s.data_size; i++) begin ##@monitor.new_bit_started; #spi_if.o_so_en <= 0b1; #await RisingEdge(self.vif.o_sclk_out) self.vif.o_mo <= tr.transfer_data self.vif.o_mo_en <= 0b1 self.vif.o_ss_en <= 0b1 await RisingEdge(self.vif.o_sclk_out) ##self.vif.o_sclk_out <= self.sclk_out; #self.vif.o_so_en <= 0b1; #uvm_info("SPI_DRIVER", $sformatf("Transfer sent :\n%s", trans.sprint()), UVM_MEDIUM) uvm_component_utils(spi_driver)
class env(UVMEnv): # gen gen1 # def __init__(self, name, parent): super().__init__(name, parent) # use the factory to create the generator self.gen1 = gen.type_id.create("gen1", self) @cocotb.coroutine def run_phase(self, phase): phase.raise_objection(self) uvm_default_tree_printer.knobs.separator = "" for i in range(5): yield Timer(15, "NS") p = self.gen1.get_packet() if hasattr(p, 'my_packet_prop') is False: uvm_fatal("PKT_ERR", "Wrong packet type created: " + str(p)) uvm_info("PKTGEN", sv.sformatf("Got packet: %s", p.sprint(uvm_default_tree_printer)), UVM_NONE) yield Timer(15, "NS") phase.drop_objection(self) # //Use the macro in a class to implement factory registration along with other # //utilities (create, get_type_name). For only factory registration, use the # // macro `uvm_component_registry(env,"env"). uvm_component_utils(env)
p = self.proto.clone() num = str(count) p.set_name(self.get_name() + "-" + num) p.set_initiator(self) if self.recording_detail != UVM_NONE: p.enable_recording(self.get_tr_stream("packet_stream")) p.randomize() uvm_info("producer", sv.sformatf("Sending %s", p.get_name()), UVM_MEDIUM) if self.uvm_report_enabled(UVM_HIGH, UVM_INFO, ""): p.print() yield self.out.put(p) yield Timer(10, "NS") uvm_info("producer", "Exiting.", UVM_MEDIUM) if self.add_objection: phase.drop_objection(self) uvm_component_utils(producer) # `uvm_field_object(proto, UVM_ALL_ON + UVM_REFERENCE) # `uvm_field_int(num_packets, UVM_ALL_ON + UVM_DEC) # `uvm_field_int(count, UVM_ALL_ON + UVM_DEC + UVM_READONLY) # `uvm_component_utils_end
@cocotb.coroutine def run_phase(self, phase): while self.out.size(): print("consumer run_phase in while-loop") p = [] yield self.out.get(p) yield self.put(p[0]) @cocotb.coroutine def put(self, p): print("consumer put() called with count " + str(self.count)) yield self.lock.get() self.count += 1 self.accept_tr(p) yield Timer(10, "NS") # #10 self.begin_tr(p) # #30; yield Timer(10, "NS") self.end_tr(p) uvm_info("consumer", sv.sformatf("Received %0s local_count=%0d", p.get_name(),self.count), UVM_MEDIUM) if self.uvm_report_enabled(UVM_HIGH,UVM_INFO,""): p.print() self.lock.put() #endclass uvm_component_utils(consumer) # `uvm_field_int(count,UVM_ALL_ON + UVM_READONLY + UVM_DEC) # `uvm_component_utils_end
# if (trans_collected.size != trans_collected.data.size()) # `uvm_error(get_type_name(), # "Transfer size field / data size mismatch.") # endfunction : check_transfer_data_size # // perform_transfer_coverage def perform_transfer_coverage(self): pass # if (trans_collected.read_write != NOP): # -> cov_transaction # for (int unsigned i = 0; i < trans_collected.size; i++): # addr = trans_collected.addr + i # data = trans_collected.data[i] # //wait_state = trans_collected.wait_state[i] # -> cov_transaction_beat # end # end # endfunction : perform_transfer_coverage #endclass : ubus_bus_monitor uvm_component_utils(ubus_bus_monitor) # // Provide implementations of virtual methods such as get_type_name and create # `uvm_component_utils_begin(ubus_bus_monitor) # `uvm_field_int(checks_enable, UVM_DEFAULT) # `uvm_field_int(coverage_enable, UVM_DEFAULT) # `uvm_field_int(num_transactions, UVM_DEFAULT) # `uvm_field_aa_object_string(slave_addr_map, UVM_DEFAULT) # `uvm_component_utils_end
uvm_fatal("TIMEOUT", "Time-out expired in post_main phase") # @cocotb.coroutine def pre_shutdown_phase(self, phase): t = [] if (UVMConfigDb.get(self, "pre_shutdown", "timeout", t) and t[0] > 0): yield Timer(t[0], "NS") uvm_fatal("TIMEOUT", "Time-out expired in pre_shutdown phase") # @cocotb.coroutine def shutdown_phase(self, phase): t = [] if (UVMConfigDb.get(self, "shutdown", "timeout", t) and t[0] > 0): yield Timer(t[0], "NS") uvm_fatal("TIMEOUT", "Time-out expired in shutdown phase") # @cocotb.coroutine def post_shutdown_phase(self, phase): t = [] if (UVMConfigDb.get(self, "post_shutdown", "timeout", t) and t[0] > 0): yield Timer(t[0], "NS") uvm_fatal("TIMEOUT", "Time-out expired in post_shutdown phase") uvm_component_utils(tb_timer) #tb_timer.m_global = tb_timer("global_timer", None)
from uvm.macros import (uvm_component_utils, uvm_fatal) from master_slave_pkg import env_top test_dur = 1200 # NS class master_slave_test(UVMTest): def __init__(self, name, parent): super().__init__(name, parent) def build_phase(self, phase): self.env = env_top("env_master_slave", self) async def run_phase(self, phase): phase.raise_objection(self) await Timer(test_dur, "NS") phase.drop_objection(self) def check_phase(self, phase): if not self.env.all_ok(): uvm_fatal("ENV_NOT_OK", "There were errors in the env") uvm_component_utils(master_slave_test) @cocotb.test() async def master_slave_top(dut): await run_test()
from uvm.base.uvm_root import UVMRoot from uvm.base.uvm_object_globals import * from uvm.base.uvm_debug import uvm_debug, UVMDebug from uvm.macros import (uvm_component_utils, uvm_fatal, uvm_error, uvm_info, uvm_component_utils_begin, uvm_component_utils_end, uvm_field_string, uvm_field_int) class DummyTest(UVMTest): def __init__(self, name="DummyTest", parent=None): super().__init__(name, parent) uvm_fatal("DUMM_TEST", "Tests fails if this test is created") uvm_component_utils(DummyTest) class CmdLineTest(UVMTest): def __init__(self, name="CmdLineTest", parent=None): super().__init__(name, parent) self.comp = None self.comp = MyComponent("my_comp", self) self.check_phase_ran = False def build_phase(self, phase): super().build_phase(phase) async def run_phase(self, phase): phase.raise_objection(self)
UVMConfigDb.set(self, "ubus0", "num_masters", num_masters) num_slaves = [] if UVMConfigDb.get(self, "ubus0", "num_slaves", num_slaves): num_slaves = num_slaves[0] else: num_slaves = 1 UVMConfigDb.set(self, "ubus0", "num_slaves", num_slaves) self.ubus0 = ubus_env.type_id.create("ubus0", self) self.scoreboard0 = ubus_example_scoreboard.type_id.create( "scoreboard0", self) # endfunction : build_phase def connect_phase(self, phase): # Connect slave0 monitor to scoreboard self.ubus0.slaves[0].monitor.item_collected_port.connect( self.scoreboard0.item_collected_export) # endfunction : connect_phase def end_of_elaboration_phase(self, phase): # Set up slave address map for ubus0 (basic default) self.ubus0.set_slave_address_map("slaves[0]", 0, 0xffff) # endfunction : end_of_elaboration_phase #endclass : ubus_example_tb uvm_component_utils(ubus_example_tb)
self.vif.tgd_i <= tr.response_data_tag await RisingEdge(self.vif.clk_i) async def get_and_drive(self, phase): tr = [] # Drives signals with sequences await self.seq_item_port.get_next_item(tr) phase.raise_objection(self, self.tag + "objection") tr = tr[0] await self.feed_data(tr) self.seq_item_port.item_done() phase.drop_objection(self, "wb_pipeline_master_driver drop objection") self.vif.ack_i <= 0 self.trig.set() async def reset_signals(self): # Hold signals low while reset self.vif.ack_i <= 0 await RisingEdge(self.vif.clk_i) async def trans_executed(self, tr): # uvm_info(self.tag, "Finished Memory Interface read to address : " + str(tr.addr.value), UVM_MEDIUM) tr.convert2string await Timer(0, "NS") uvm_component_utils(wb_pipeline_master_driver)