def adjust_vs3_rs1_rs2_vm(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) reg_count = 1 if "SEG" in aInstruction.name: src_opr = aInstruction.find_operand("vs3") reg_count = int(src_opr.regCount) operand_adjustor.set_vs3() operand_adjustor.set_rs1_int_ls_base() operand_adjustor.set_rs2_int_ls_base() width = get_element_size(aInstruction.find_operand("const_bits")) attr_dict = dict() subop_dict = dict() subop_dict["base"] = "rs1" subop_dict["index"] = "rs2" attr_dict["alignment"] = width attr_dict["base"] = "rs1" attr_dict["data-size"] = width * reg_count attr_dict["element-size"] = width attr_dict["mem-access"] = "Write" add_addressing_operand( aInstruction, None, "LoadStore", "VectorStridedLoadStoreOperandRISCV", subop_dict, attr_dict, ) operand_adjustor.set_vm() return True
def adjust_rs1_vs2_vs3_vm(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) operand_adjustor.set_rs1_int_ls_base() operand_adjustor.set_vs2() operand_adjustor.set_vs2_differ_vs3() width = get_element_size(aInstruction.find_operand("const_bits")) attr_dict = dict() subop_dict = dict() subop_dict["base"] = "rs1" subop_dict["index"] = "vs2" attr_dict["base"] = "rs1" attr_dict["mem-access"] = "ReadWrite" add_addressing_operand( aInstruction, None, "LoadStore", "VectorIndexedLoadStoreOperandRISCV", subop_dict, attr_dict, ) operand_adjustor.set_vs3() operand_adjustor.set_vm() return True
def adjust_vs3_rs1_vm(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) operand_adjustor.set_vs3() operand_adjustor.set_rs1_int_ls_base() width = get_element_size(aInstruction.find_operand("const_bits")) attr_dict = dict() subop_dict = dict() subop_dict["base"] = "rs1" attr_dict["alignment"] = width attr_dict["base"] = "rs1" attr_dict["element-size"] = width attr_dict["mem-access"] = "Write" add_addressing_operand( aInstruction, None, "LoadStore", "VectorBaseOffsetLoadStoreOperandRISCV", subop_dict, attr_dict, ) operand_adjustor.set_vm() return True