def generate_top_inout_wires(top_module):
buf = "//Master inout wires\n"
if "inout" in top_module["ports"]:
for port in top_module["ports"]["inout"]:
buf += vutils.create_wire_buf_from_dict(port, top_module["ports"]["inout"][port])
return buf
def generate_sub_module_wires(self, invert_reset, instance_name, module_tags):
#Add all input and output wires to the ports
buf = ""
if "input" in module_tags["ports"]:
buf += "//inputs\n"
for port in module_tags["ports"]["input"]:
if port == "clk":
continue
if port == "rst":
continue
pname = port
if len(instance_name) > 0:
pname = "%s_%s" % (instance_name, port)
if self.in_wires(pname, module_tags["ports"]["input"][port]):
continue
if module_tags["module"] == "top":
buf += vutils.create_reg_buf_from_dict(pname,
module_tags["ports"]["input"][port])
else:
buf += vutils.create_wire_buf_from_dict(pname,
module_tags["ports"]["input"][port])
self.add_wire(pname, module_tags["ports"]["input"][port])
buf += "\n"
if "output" in module_tags["ports"]:
buf += "//outputs\n"
for port in module_tags["ports"]["output"]:
pname = port
if len(instance_name) > 0:
pname = "%s_%s" % (instance_name, port)
if self.in_wires(pname, module_tags["ports"]["output"][port]):
continue
buf += vutils.create_wire_buf_from_dict(pname,
module_tags["ports"]["output"][port])
self.add_wire(pname, module_tags["ports"]["output"][port])
buf += "\n"
return buf
def generate_sub_module_wires(self, invert_reset, instance_name,
module_tags):
#Add all input and output wires to the ports
buf = ""
if "input" in module_tags["ports"]:
buf += "//inputs\n"
for port in module_tags["ports"]["input"]:
if port == "clk":
continue
if port == "rst":
continue
pname = port
if len(instance_name) > 0:
pname = "%s_%s" % (instance_name, port)
if self.in_wires(pname, module_tags["ports"]["input"][port]):
continue
buf += vutils.create_wire_buf_from_dict(
pname, module_tags["ports"]["input"][port])
self.add_wire(pname, module_tags["ports"]["input"][port])
buf += "\n"
if "output" in module_tags["ports"]:
buf += "//outputs\n"
for port in module_tags["ports"]["output"]:
pname = port
if len(instance_name) > 0:
pname = "%s_%s" % (instance_name, port)
if self.in_wires(pname, module_tags["ports"]["output"][port]):
continue
buf += vutils.create_wire_buf_from_dict(
pname, module_tags["ports"]["output"][port])
self.add_wire(pname, module_tags["ports"]["output"][port])
buf += "\n"
return buf
