def __init__(self, m, name, prefix, clk, rst, txd=None,
arg_params=None, arg_ports=None,
as_io=None, as_wire=None,
baudrate=19200, clockfreq=100 * 1000 * 1000):
if arg_ports is None:
arg_ports = []
arg_ports.insert(0, ('CLK', clk))
arg_ports.insert(1, ('RST', rst))
if txd is not None:
arg_ports.insert(2, ('txd', txd))
moddef = mkUartTx(baudrate, clockfreq)
Submodule.__init__(self, m, moddef, name, prefix,
arg_params=arg_params, arg_ports=arg_ports,
as_io=as_io, as_wire=as_wire)
self.tx_din = self['din']
self.tx_enable = self['enable']
self.tx_enable.initval = 0
self.tx_ready = self['ready']
self.mutex = None
def __init__(self,
m,
name,
prefix,
clk,
rst,
txd=None,
arg_params=None,
arg_ports=None,
as_io=None,
as_wire=None,
baudrate=19200,
clockfreq=100 * 1000 * 1000):
if arg_ports is None:
arg_ports = []
arg_ports.insert(0, ('CLK', clk))
arg_ports.insert(1, ('RST', rst))
if txd is not None:
arg_ports.insert(2, ('txd', txd))
moddef = mkUartTx(baudrate, clockfreq)
Submodule.__init__(self,
m,
moddef,
name,
prefix,
arg_params=arg_params,
arg_ports=arg_ports,
as_io=as_io,
as_wire=as_wire)
self.tx_din = self['din']
self.tx_enable = self['enable']
self.tx_enable.initval = 0
self.tx_ready = self['ready']
self.mutex = None
def __init__(self,
m,
name,
prefix,
clk,
rst,
rxd=None,
arg_params=None,
arg_ports=None,
as_io=None,
as_wire=None,
baudrate=19200,
clockfreq=100 * 1000 * 1000):
if arg_ports is None:
arg_ports = []
arg_ports.insert(0, ('CLK', clk))
arg_ports.insert(1, ('RST', rst))
if rxd is not None:
arg_ports.insert(2, ('rxd', rxd))
moddef = mkUartRx(baudrate, clockfreq)
Submodule.__init__(self,
m,
moddef,
name,
prefix,
arg_params=arg_params,
arg_ports=arg_ports,
as_io=as_io,
as_wire=as_wire)
self.rx_dout = self['dout']
self.rx_valid = self['valid']
self.mutex = None
def __init__(self, m, name, prefix, clk, rst, rxd=None,
arg_params=None, arg_ports=None,
as_io=None, as_wire=None,
baudrate=19200, clockfreq=100 * 1000 * 1000):
if arg_ports is None:
arg_ports = []
arg_ports.insert(0, ('CLK', clk))
arg_ports.insert(1, ('RST', rst))
if rxd is not None:
arg_ports.insert(2, ('rxd', rxd))
moddef = mkUartRx(baudrate, clockfreq)
Submodule.__init__(self, m, moddef, name, prefix,
arg_params=arg_params, arg_ports=arg_ports,
as_io=as_io, as_wire=as_wire)
self.rx_dout = self['dout']
self.rx_valid = self['valid']
self.mutex = None
elif not reset or rst is None:
m.Always(vtypes.Posedge(clk))(body, )
else:
m.Always(vtypes.Posedge(clk))(vtypes.If(rst)(reset, )(body, ))
arg_params = [(name, param) for name, param in params.items()]
arg_ports = [('CLK', self.clk)]
if self.rst is not None:
arg_ports.append(('RST', self.rst))
arg_ports.extend([(name, port) for name, port in ports.items()])
sub = Submodule(self.m,
m,
'inst_' + m.name,
'_%s_' % self.name,
arg_params=arg_params,
arg_ports=arg_ports)
#-------------------------------------------------------------------------
def make_case(self):
indexes = set(self.body.keys())
indexes.update(set(self.jump.keys()))
for index in indexes:
self._add_mark(index)
ret = []
ret.extend(self.seq.make_code())
ret.extend(self._get_delayed_substs())
def make_module(self, reset=(), body=()):
if self.done:
#raise ValueError('make_always() has been already called.')
return
self.done = True
m = Module(self.name)
clk = m.Input('CLK')
if self.rst is not None:
rst = m.Input('RST')
else:
rst = None
body = list(body) + list(self.make_code())
dsts = self.dst_var.values()
src_visitor = SubstSrcVisitor()
# collect sources in destination variable definitions
for dst in dsts:
if isinstance(dst, (vtypes.Pointer, vtypes.Slice, vtypes.Cat)):
raise ValueError(
'Partial assignment is not supported by as_module mode.')
if isinstance(dst, vtypes._Variable):
if dst.width is not None:
src_visitor.visit(dst.width)
if dst.length is not None:
src_visitor.visit(dst.length)
# collect sources in statements
for statement in body:
src_visitor.visit(statement)
srcs = src_visitor.srcs.values()
# collect sources in source variable definitions
for src in srcs:
if isinstance(src, vtypes._Variable):
if src.width is not None:
src_visitor.visit(src.width)
if src.length is not None:
src_visitor.visit(src.length)
srcs = src_visitor.srcs.values()
params = collections.OrderedDict()
ports = collections.OrderedDict()
src_rename_dict = collections.OrderedDict()
# create parameter/localparam definitions
for src in srcs:
if isinstance(src, (vtypes.Parameter, vtypes.Localparam)):
arg_name = src.name
v = m.Parameter(arg_name, src.value, src.width, src.signed)
src_rename_dict[src.name] = v
params[arg_name] = src
src_rename_visitor = SrcRenameVisitor(src_rename_dict)
for src in srcs:
if isinstance(src, (vtypes.Parameter, vtypes.Localparam)):
continue
arg_name = 'i_%s' % src.name
if src.length is not None:
width = src.bit_length()
length = src.length
pack_width = vtypes.Mul(width, length)
out_line = self.m.TmpWire(
pack_width, prefix='_%s_%s' % (self.name, src.name))
i = self.m.TmpGenvar(prefix='i')
v = out_line[i * width:(i + 1) * width]
g = self.m.GenerateFor(i(0), i < length, i(i + 1))
p = g.Assign(v(src[i]))
rep_width = (src_rename_visitor.visit(src.width)
if src.width is not None else None)
rep_length = src_rename_visitor.visit(src.length)
pack_width = (rep_length if rep_width is None else
vtypes.Mul(rep_length, rep_width))
in_line = m.Input(arg_name + '_line', pack_width,
signed=src.get_signed())
in_array = m.Wire(arg_name, rep_width, rep_length,
signed=src.get_signed())
i = m.TmpGenvar(prefix='i')
v = in_line[i * rep_width:(i + 1) * rep_width]
g = m.GenerateFor(i(0), i < rep_length, i(i + 1))
p = g.Assign(in_array[i](v))
src_rename_dict[src.name] = in_array
ports[in_line.name] = out_line
else:
rep_width = (src_rename_visitor.visit(src.width)
if src.width is not None else None)
v = m.Input(arg_name, rep_width, signed=src.get_signed())
src_rename_dict[src.name] = v
ports[arg_name] = src
for dst in dsts:
arg_name = dst.name
rep_width = (src_rename_visitor.visit(dst.width)
if dst.width is not None else None)
out = m.OutputReg(arg_name, rep_width, signed=dst.get_signed())
out_wire = self.m.TmpWire(rep_width, signed=dst.get_signed(),
prefix='_%s_%s' % (self.name, arg_name))
self.m.Always()(dst(out_wire, blk=True))
ports[arg_name] = out_wire
body = [src_rename_visitor.visit(statement)
for statement in body]
reset = list(reset) + list(self.make_reset())
if not reset and not body:
pass
elif not reset or rst is None:
m.Always(vtypes.Posedge(clk))(
body,
)
else:
m.Always(vtypes.Posedge(clk))(
vtypes.If(rst)(
reset,
)(
body,
))
arg_params = [(name, param) for name, param in params.items()]
arg_ports = [('CLK', self.clk)]
if self.rst is not None:
arg_ports.append(('RST', self.rst))
arg_ports.extend([(name, port) for name, port in ports.items()])
sub = Submodule(self.m, m, 'inst_' + m.name, '_%s_' % self.name,
arg_params=arg_params, arg_ports=arg_ports)