def mkUartTx(baudrate=19200, clockfreq=100 * 1000 * 1000):
m = Module("UartTx")
waitnum = int(clockfreq / baudrate)
clk = m.Input('CLK')
rst = m.Input('RST')
din = m.Input('din', 8)
enable = m.Input('enable')
ready = m.OutputReg('ready', initval=1)
txd = m.OutputReg('txd', initval=1)
fsm = FSM(m, 'fsm', clk, rst)
mem = m.TmpReg(9, initval=0)
waitcount = m.TmpReg(int(math.log(waitnum, 2)) + 1, initval=0)
fsm(
waitcount(waitnum - 1),
txd(1),
mem(vtypes.Cat(din, vtypes.Int(0, 1)))
)
fsm.If(enable)(
ready(0)
)
fsm.Then().goto_next()
for i in range(10):
fsm.If(waitcount > 0)(
waitcount.dec()
).Else(
txd(mem[0]),
mem(vtypes.Cat(vtypes.Int(1, 1), mem[1:9])),
waitcount(waitnum - 1)
)
fsm.Then().goto_next()
fsm(
ready(1)
)
fsm.goto_init()
fsm.make_always()
return m
def mkUartRx(baudrate=19200, clockfreq=100 * 1000 * 1000):
m = Module("UartRx")
waitnum = int(clockfreq / baudrate)
clk = m.Input('CLK')
rst = m.Input('RST')
rxd = m.Input('rxd')
dout = m.OutputReg('dout', 8, initval=0)
valid = m.OutputReg('valid', initval=0)
fsm = FSM(m, 'fsm', clk, rst)
mem = m.TmpReg(9, initval=0)
waitcount = m.TmpReg(int(math.log(waitnum, 2)) + 1, initval=0)
fsm(
valid(0),
waitcount(int(waitnum / 2) - 1),
mem(vtypes.Cat(rxd, mem[1:9]))
)
fsm.If(rxd == 0).goto_next()
for i in range(10):
if i == 0: # check the start bit again
fsm.If(vtypes.Ands(waitcount == 1, rxd != 0)).goto_init()
fsm.If(waitcount > 0)(
waitcount.dec()
).Else(
mem(vtypes.Cat(rxd, mem[1:9])),
waitcount(waitnum - 1)
)
fsm.Then().goto_next()
fsm(
valid(1),
dout(mem[0:9])
)
fsm.goto_init()
fsm.make_always()
return m
def mkUartRx(baudrate=19200, clockfreq=100 * 1000 * 1000):
m = Module("UartRx")
waitnum = int(clockfreq / baudrate)
clk = m.Input('CLK')
rst = m.Input('RST')
rxd = m.Input('rxd')
dout = m.OutputReg('dout', 8, initval=0)
valid = m.OutputReg('valid', initval=0)
fsm = FSM(m, 'fsm', clk, rst)
mem = m.TmpReg(9, initval=0)
waitcount = m.TmpReg(int(math.log(waitnum, 2)) + 1, initval=0)
fsm(valid(0), waitcount(int(waitnum / 2) - 1),
mem(vtypes.Cat(rxd, mem[1:9])))
fsm.If(rxd == 0).goto_next()
for i in range(10):
if i == 0: # check the start bit again
fsm.If(vtypes.Ands(waitcount == 1, rxd != 0)).goto_init()
fsm.If(waitcount > 0)(waitcount.dec()).Else(
mem(vtypes.Cat(rxd, mem[1:9])), waitcount(waitnum - 1))
fsm.Then().goto_next()
fsm(valid(1), dout(mem[0:9]))
fsm.goto_init()
fsm.make_always()
return m
def mkUartTx(baudrate=19200, clockfreq=100 * 1000 * 1000):
m = Module("UartTx")
waitnum = int(clockfreq / baudrate)
clk = m.Input('CLK')
rst = m.Input('RST')
din = m.Input('din', 8)
enable = m.Input('enable')
ready = m.OutputReg('ready', initval=1)
txd = m.OutputReg('txd', initval=1)
fsm = FSM(m, 'fsm', clk, rst)
mem = m.TmpReg(9, initval=0)
waitcount = m.TmpReg(int(math.log(waitnum, 2)) + 1, initval=0)
fsm(waitcount(waitnum - 1), txd(1), mem(vtypes.Cat(din, vtypes.Int(0, 1))))
fsm.If(enable)(ready(0))
fsm.Then().goto_next()
for i in range(10):
fsm.If(waitcount > 0)(waitcount.dec()).Else(
txd(mem[0]), mem(vtypes.Cat(vtypes.Int(1, 1), mem[1:9])),
waitcount(waitnum - 1))
fsm.Then().goto_next()
fsm(ready(1))
fsm.goto_init()
fsm.make_always()
return m