def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiMaster(m, 'myaxi', clk, rst)
myaxi.disable_read()
fsm = FSM(m, 'fsm', clk, rst)
# write address
awaddr = 1024
awlen = 64
ack, counter = myaxi.write_request(awaddr, awlen, cond=fsm)
fsm.If(ack).goto_next()
# write data
wdata = m.Reg('wdata', 32, initval=0)
ack, last = myaxi.write_data(wdata, counter, cond=fsm)
fsm.If(ack)(wdata.inc())
fsm.If(last).goto_next()
sum = m.Reg('sum', 32, initval=0)
expected_sum = (awlen - 1) * awlen // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(Ands(myaxi.wdata.wvalid,
myaxi.wdata.wready))(sum.add(myaxi.wdata.wdata))
seq.Then().If(myaxi.wdata.wlast).Delay(1)(Systask(
'display', "sum=%d expected_sum=%d", sum, expected_sum))
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiMaster(m, 'myaxi', clk, rst)
myaxi.disable_write()
df = dataflow.DataflowManager(m, clk, rst)
req_fsm = FSM(m, 'req_fsm', clk, rst)
# read request
araddr = 1024
arlen = 64
ack, counter = myaxi.read_request(araddr, arlen, cond=req_fsm)
req_fsm.If(ack).goto_next()
# read dataflow (AXI -> Dataflow)
data, last, done = myaxi.read_dataflow()
sum = df.ReduceAdd(data, reset=last.prev(1))
# verify
sum_data, sum_valid = sum.read()
last_data, last_valid = last.read()
expected_sum = ((araddr + araddr + arlen - 1) * arlen) // 2
data_seq = Seq(m, 'data_seq', clk, rst)
data_seq.If(Ands(sum_valid, last_valid, last_data == 1)).Delay(1)(
Systask('display', 'sum=%d expected_sum=%d', sum_data, expected_sum)
)
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiMaster(m, 'myaxi', clk, rst)
myaxi.disable_write()
fsm = FSM(m, 'fsm', clk, rst)
sum = m.Reg('sum', 32, initval=0)
# read address
araddr = 1024
arlen = 64
expected_sum = (araddr + araddr + arlen - 1) * arlen // 2
ack, counter = myaxi.read_request_counter(araddr, arlen, cond=fsm)
fsm.If(ack).goto_next()
# read data
data, valid, last = myaxi.read_data(counter, cond=fsm)
fsm.If(valid)(sum(sum + data))
fsm.Then().If(last).goto_next()
fsm(Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum))
fsm.goto_next()
fsm.make_always()
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiMaster(m, 'myaxi', clk, rst)
myram = RAM(m, 'myram', clk, rst, numports=1)
df = dataflow.DataflowManager(m, clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# AXI read request
araddr = 1024
arlen = 64
ack, counter = myaxi.read_request_counter(araddr, arlen, cond=fsm)
fsm.If(ack).goto_next()
# AXI read dataflow (AXI -> Dataflow)
axi_data, axi_last, done = myaxi.read_dataflow()
sum = df.ReduceAdd(axi_data, reset=axi_last.prev(1))
# RAM write dataflow (Dataflow -> RAM)
wport = 0
waddr = 0
wlen = arlen
done = myram.write_dataflow(wport, waddr, sum, wlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
# AXI write request
awaddr = 1024
awlen = 64
ack, counter = myaxi.write_request_counter(awaddr, awlen, cond=fsm)
fsm.If(ack).goto_next()
# RAM read dataflow (RAM -> Dataflow)
rport = 0
raddr = 0
rlen = arlen
rdata, rlast, done = myram.read_dataflow(rport, raddr, rlen, cond=fsm)
fsm.goto_next()
# AXI write dataflow
done = myaxi.write_dataflow(rdata, counter)
fsm.If(done).goto_next()
# verify
sum = m.Reg('sum', 32, initval=0)
expected_sum = 0
for i in range(arlen):
expected_sum += (araddr + araddr + i) * (i + 1) // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(Ands(myaxi.wdata.wvalid,
myaxi.wdata.wready))(sum.add(myaxi.wdata.wdata))
seq.Then().If(myaxi.wdata.wlast).Delay(1)(Systask(
'display', "sum=%d expected_sum=%d", sum, expected_sum))
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiMaster(m, 'myaxi', clk, rst)
myaxi.disable_read()
fsm = FSM(m, 'fsm', clk, rst)
# write address
awaddr = 1024
awlen = 64
ack, counter0 = myaxi.write_request(awaddr, awlen, cond=fsm)
fsm.If(ack).goto_next()
awaddr = 1024 * 2
awlen = 64
ack, counter1 = myaxi.write_request(awaddr, awlen, cond=fsm)
fsm.If(ack).goto_next()
# write data
wdata = m.Reg('wdata', 32, initval=0)
first = fsm.current
ack, last = myaxi.write_data(wdata, counter0, cond=fsm)
fsm.If(ack)(wdata.inc())
fsm.If(last).goto_next()
fsm(wdata(1000))
fsm.goto_next()
for i in range(8):
fsm.goto_next()
second = fsm.current
for i in range(8):
fsm.goto_next()
ack, last = myaxi.write_data(wdata, counter1, cond=fsm)
fsm.If(ack)(wdata.inc())
fsm.If(last).goto_next()
sum = m.Reg('sum', 32, initval=0)
expected_sum0 = (awlen - 1) * awlen // 2
expected_sum1 = (1000 + 1000 + awlen - 1) * awlen // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(fsm.state == second)(sum(0))
seq.If(Ands(myaxi.wdata.wvalid,
myaxi.wdata.wready))(sum.add(myaxi.wdata.wdata), )
seq.Then().If(myaxi.wdata.wlast).Delay(1)(If(fsm.state < second)(Systask(
'display', "sum=%d expected_sum=%d", sum, expected_sum0)).Else(
Systask('display', "sum=%d expected_sum=%d", sum, expected_sum1)))
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiMaster(m, 'myaxi', clk, rst)
myaxi.disable_write()
myram = RAM(m, 'myram', clk, rst, numports=1)
df = dataflow.DataflowManager(m, clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# AXI read request
araddr = 1024
arlen = 64
ack, axi_counter = myaxi.read_request_counter(araddr, arlen, cond=fsm)
fsm.If(ack).goto_next()
# AXI read dataflow (AXI -> Dataflow)
axi_data, axi_last, done = myaxi.read_dataflow()
sum = df.ReduceAdd(axi_data, reset=axi_last.prev(1))
# RAM write dataflow (Dataflow -> RAM)
wport = 0
waddr = 0
wlen = arlen
done = myram.write_dataflow(wport, waddr, sum, wlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
# verify
# read dataflow (RAM -> Dataflow)
rport = 0
raddr = 0
rlen = arlen
rdata, rlast, done = myram.read_dataflow(rport, raddr, rlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
rdata_data, rdata_valid = rdata.read()
rlast_data, rlast_valid = rlast.read()
sum = m.Reg('sum', 32, initval=0)
expected_sum = 0
for i in range(arlen):
expected_sum += (araddr + araddr + i) * (i + 1) // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(rdata_valid)(sum.add(rdata_data))
seq.Then().If(rlast_data == 1).Delay(1)(
Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum),
If(NotEql(sum, expected_sum))(Display('# verify: FAILED')).Else(
Display('# verify: PASSED')))
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiMaster(m, 'myaxi', clk, rst)
myaxi.disable_read()
fsm = FSM(m, 'fsm', clk, rst)
# write address (1)
awaddr = 1024
awlen = 64
ack, counter = myaxi.write_request_counter(awaddr, awlen, cond=fsm)
fsm.If(ack).goto_next()
# write data (1)
wdata = m.Reg('wdata', 32, initval=0)
ack, last = myaxi.write_data(wdata, counter, cond=fsm)
fsm.If(ack)(
wdata.inc()
)
fsm.If(last).goto_next()
# write address (2)
ack, counter = myaxi.write_request_counter(awaddr, awlen, cond=fsm)
fsm.If(ack).goto_next()
# write data (2)
ack, last = myaxi.write_data(wdata, counter, cond=fsm)
fsm.If(ack)(
wdata.inc()
)
fsm.If(last).goto_next()
# check
sum = m.Reg('sum', 32, initval=0)
expected_sum = (awlen * 2 - 1) * (awlen * 2) // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(Ands(myaxi.wdata.wvalid, myaxi.wdata.wready))(
sum.add(myaxi.wdata.wdata)
)
seq.Then().If(myaxi.wdata.wlast).Delay(1)(
Systask('display', "current_sum=%d expected_sum=%d", sum, expected_sum),
If(fsm.here)(If(NotEql(sum, expected_sum))(Display('# verify: FAILED')).Else(Display('# verify: PASSED')))
)
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
led = m.Output('LED', 32)
myaxi = axi.AxiMaster(m, 'myaxi', clk, rst)
myaxi.disable_write()
fsm = FSM(m, 'fsm', clk, rst)
sum = m.Reg('sum', 32, initval=0)
led.assign(sum)
# read address (1)
araddr = 1024
arlen = 64
expected_sum = (araddr // 4 + araddr // 4 + arlen - 1) * arlen // 2
ack, counter = myaxi.read_request_counter(araddr, arlen, cond=fsm)
fsm.If(ack).goto_next()
# read data (1)
data, valid, last = myaxi.read_data(counter, cond=fsm)
fsm.If(valid)(sum(sum + data))
fsm.Then().If(last).goto_next()
# read address (2)
araddr = 1024 + 1024
arlen = 64
expected_sum += (araddr // 4 + araddr // 4 + arlen - 1) * arlen // 2
ack, counter = myaxi.read_request_counter(araddr, arlen, cond=fsm)
fsm.If(ack).goto_next()
# read data (2)
data, valid, last = myaxi.read_data(counter, cond=fsm)
fsm.If(valid)(sum(sum + data))
fsm.Then().If(last).goto_next()
fsm(
Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum),
If(NotEql(sum, expected_sum))(Display('# verify: FAILED')).Else(
Display('# verify: PASSED')))
fsm.goto_next()
fsm.make_always()
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiMaster(m, 'myaxi', clk, rst)
myaxi.disable_read()
df = dataflow.DataflowManager(m, clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# write request
awaddr = 1024
awlen = 64
ack, counter = myaxi.write_request(awaddr, awlen, cond=fsm)
fsm.If(ack).goto_next()
# dataflow
c = df.Counter()
value = c - 1
t = df.Counter(maxval=8).prev(1)
when = t == 0
# write dataflow (Dataflow -> AXI)
done = myaxi.write_dataflow(value, counter, when=when)
fsm.If(done).goto_next()
# verify
sum = m.Reg('sum', 32, initval=0)
expected_sum = 8 * (awlen - 1) * awlen // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(Ands(myaxi.wdata.wvalid, myaxi.wdata.wready))(
sum.add(myaxi.wdata.wdata),
)
seq.Then().If(myaxi.wdata.wlast).Delay(1)(
Systask('display', "sum=%d expected_sum=%d", sum, expected_sum)
)
return m
def mkTest():
m = Module('test')
# target instance
main = mkMain()
# copy paras and ports
params = m.copy_params(main)
ports = m.copy_sim_ports(main)
sum = ports['sum']
clk = ports['CLK']
rst = ports['RST']
_axi = axi.AxiMaster(m, '_axi', clk, rst, noio=True)
_axi.connect(ports, 'myaxi')
fsm = FSM(m, 'fsm', clk, rst)
rsum = m.Reg('rsum', 32, initval=0)
# read address (1)
araddr = 1024
arlen = 64
expected_rsum = (araddr // 4 + araddr // 4 + arlen - 1) * arlen // 2
ack, counter = _axi.read_request(araddr, arlen, cond=fsm)
fsm.If(ack).goto_next()
# read data (1)
data, valid, last = _axi.read_data(counter, cond=fsm)
fsm.If(valid)(rsum(rsum + data))
fsm.Then().If(last).goto_next()
# read address (2)
araddr = 1024 + 1024
arlen = 128
expected_rsum += (araddr // 4 + araddr // 4 + arlen - 1) * arlen // 2
ack, counter = _axi.read_request(araddr, arlen, cond=fsm)
fsm.If(ack).goto_next()
# read data (2)
data, valid, last = _axi.read_data(counter, cond=fsm)
fsm.If(valid)(rsum(rsum + data))
fsm.Then().If(last).goto_next()
fsm(Systask('display', 'rsum=%d expected_rsum=%d', rsum, expected_rsum))
fsm.goto_next()
# write address (1)
awaddr = 1024
awlen = 64
expected_sum = ((0 + (awlen - 1)) * awlen) // 2
ack, counter = _axi.write_request(awaddr, awlen, cond=fsm)
fsm.If(ack).goto_next()
# write data (1)
wdata = m.Reg('wdata', 32, initval=0)
ack, last = _axi.write_data(wdata, counter, cond=fsm)
fsm.If(ack)(wdata.inc())
fsm.If(last).goto_next()
# write address (2)
prev_awlen = awlen
awlen = 128
expected_sum += ((prev_awlen + (prev_awlen + awlen - 1)) * awlen) // 2
ack, counter = _axi.write_request(awaddr, awlen, cond=fsm)
fsm.If(ack).goto_next()
# write data (2)
ack, last = _axi.write_data(wdata, counter, cond=fsm)
fsm.If(ack)(wdata.inc())
fsm.If(last).goto_next()
fsm(Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum))
fsm.goto_next()
uut = m.Instance(main,
'uut',
params=m.connect_params(main),
ports=m.connect_ports(main))
simulation.setup_waveform(m, uut, m.get_vars())
simulation.setup_clock(m, clk, hperiod=5)
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
init.add(
Delay(1000 * 100),
Systask('finish'),
)
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
# AXI ports
slave = axi.AxiSlave(m, 'slave', clk, rst)
master = axi.AxiMaster(m, 'master', clk, rst)
# a, b: source, c: result
ram_a = ram.SyncRAMManager(m, 'ram_a', clk, rst, numports=1)
ram_b = ram.SyncRAMManager(m, 'ram_b', clk, rst, numports=1)
ram_c = ram.SyncRAMManager(m, 'ram_c', clk, rst, numports=1)
read_fsm = FSM(m, 'read_fsm', clk, rst)
write_fsm = FSM(m, 'write_fsm', clk, rst)
df = dataflow.DataflowManager(m, clk, rst)
# df.enable_draw_graph()
read_fsm.goto_next()
row_count = m.Reg('row_count', 32, initval=0)
read_fsm(row_count(0))
# wait for slave request
slave_addr, slave_counter, slave_valid = slave.pull_write_request(
cond=read_fsm)
read_fsm.If(slave_valid).goto_next()
data, mask, valid, last = slave.pull_write_data(slave_counter,
cond=read_fsm)
read_fsm.If(valid).goto_next()
write_fsm.If(read_fsm).goto_next()
# computation
master_addr = 1024 * 2
ram_addr = 0
length = 16
dma_done = master.dma_read(ram_b,
master_addr,
ram_addr,
length,
cond=read_fsm)
read_fsm.If(dma_done).goto_next()
comp_start = read_fsm.current
master_addr = 1024
ram_addr = 0
length = 16
dma_done = master.dma_read(ram_a,
master_addr,
ram_addr,
length,
cond=read_fsm)
read_fsm.If(dma_done).goto_next()
adata, alast, adone = ram_a.read_dataflow(0,
ram_addr,
length,
cond=read_fsm)
bdata, blast, bdone = ram_b.read_dataflow(0,
ram_addr,
length,
cond=read_fsm)
read_fsm.goto_next()
mul = adata * bdata
mul_count = df.Counter(maxval=length)
wcond = mul_count == 0
cdata = df.Iadd(mul, reset=wcond.prev(1))
read_fsm(row_count.inc())
read_fsm.If(row_count < length - 1).goto(comp_start)
read_fsm.If(row_count == length - 1).goto_next()
done = ram_c.write_dataflow(0,
0,
cdata,
length,
cond=write_fsm,
when=wcond)
write_fsm.goto_next()
write_fsm.If(done).goto_next()
master_addr = 1024 * 3
dma_done = master.dma_write(ram_c,
master_addr,
ram_addr,
length,
cond=write_fsm)
write_fsm.If(dma_done).goto_next()
read_fsm.If(write_fsm).goto_init()
write_fsm.goto_init()
seq = Seq(m, 'seq', clk, rst)
seq.If(ram_c[0].wenable)(Systask('display', '[%d]<-%d', ram_c[0].addr,
ram_c[0].wdata))
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
slave = axi.AxiSlave(m, 'slave', clk, rst)
master = axi.AxiMaster(m, 'master', clk, rst)
ram_a = bram.Bram(m, 'ram_a', clk, rst, numports=1)
ram_b = bram.Bram(m, 'ram_b', clk, rst, numports=1)
ram_c = bram.Bram(m, 'ram_c', clk, rst, numports=1)
fsm = FSM(m, 'fsm', clk, rst)
# wait for slave request
slave_addr, slave_counter, slave_valid = slave.pull_write_request(cond=fsm)
fsm.If(slave_valid).goto_next()
data, mask, valid, last = slave.pull_write_data(slave_counter, cond=fsm)
fsm.If(valid).goto_next()
# computation
master_addr = 1024
ram_addr = 0
length = 64
dma_done = master.dma_read(ram_a, master_addr, ram_addr, length, cond=fsm)
fsm.If(dma_done).goto_next()
master_addr = 1024 * 2
dma_done = master.dma_read(ram_b, master_addr, ram_addr, length, cond=fsm)
fsm.If(dma_done).goto_next()
adata, alast, adone = ram_a.read_dataflow(0, ram_addr, length, cond=fsm)
bdata, blast, bdone = ram_b.read_dataflow(0, ram_addr, length, cond=fsm)
cdata = adata + bdata
done = ram_c.write_dataflow(0, ram_addr, cdata, length, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
master_addr = 1024 * 3
dma_done = master.dma_write(ram_c, master_addr, ram_addr, length, cond=fsm)
fsm.If(dma_done).goto_next()
# checksum
sum = m.Reg('sum', 32, initval=0)
expected_sum = (((1024 + 1024 + 63) * 64 // 2) +
((1024 * 2 + 1024 * 2 + 63) * 64 // 2))
seq = Seq(m, 'seq', clk, rst)
seq.If(fsm.state == 0)(sum(0))
seq.If(master.wdata.wvalid,
master.wdata.wready)(sum(sum + master.wdata.wdata))
seq.If(master.wdata.wvalid, master.wdata.wready,
master.wdata.wlast).Delay(1)(Systask('display',
"sum=%d expected_sum=%d", sum,
expected_sum))
fsm.If(master.wdata.wvalid, master.wdata.wready,
master.wdata.wlast).Delay(1).goto_next()
# return the checksum
slave_addr, slave_counter, slave_valid = slave.pull_read_request(cond=fsm)
fsm.If(slave_valid).goto_next()
ack, last = slave.push_read_data(sum, slave_counter, cond=fsm)
fsm.If(last).goto_next()
# repeat
fsm.goto_init()
return m