print pu.parse_assignment_split('add r7, sp')
print pu.parse_assignment_split('str r0, [r4, r5]')
print 'register: %s' % pu.parse_register(
' r2 ; XREF=0x31ae')
print pu.parse_stack_push_via_stm('stm.w sp, {r3, r11}',
cpu.stack_pointer_register())
print pu.parse_stack_push_via_stm('stm.w sp, {r2, r9}',
cpu.stack_pointer_register().register)
print pu.parse_stack_access('[sp, #0x8]')
print pu.parse_stack_access('[sp]')
print pu.parse_offset_addring_offset_needed('[r0, r4]')
print pu.parse_offset_addressing('[r0]')
# VarAssignment test
cpu.memory.registers.set_value_for_register(
reg('r5'),
IVar(ObjcClass('SelfClass'),
MsgSend(ObjcClass('Foo'),
[Selector('alloc'), Selector('init')])))
cpu.memory.registers.set_value_for_register(reg('r0'), ObjcClass('Foo'))
cpu.memory.registers.set_value_for_register(reg('r4'),
ObjcClass('SelfClass'))
print pu.parse_var_assignment_with_ivar_ref_from_asmline(
'str r0, [r4, r5]')
print pu.parse_var_assignment_without_ivar_ref_from_asmline('[sp, r5]')
print pu.parse_var_assignment_with_ivar_ref_from_asmline(
'str r0, [sp, r5]')
print 'stack access: %s' % str(pu.parse_stack_access('[sp, #0x4]'))
print 'stack access: %s' % str(pu.parse_stack_access('[sp], #0x4'))
print 'stack access: %s' % str(pu.parse_stack_access('[sp]'))
def frame_pointer_register(self):
return reg('r7')
def stack_pointer_register(self):
return reg('sp')
def return_register(self):
return reg('r0')
def selector_register(self):
return reg('r1')
def destination_register(self):
return reg('r0')